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Commit 5bd5bce5 authored by Adam Ford's avatar Adam Ford Committed by Tony Lindgren
Browse files

ARM: dts: am3517-evm: Enable USB1 Host 



The AM3517-evm has a single USB Host port connected to hsusb1.
This patch enables that USB port.

Signed-off-by: default avatarAdam Ford <aford173@gmail.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 19054d0a

arch/arm/boot/dts/am3517-evm.dts

+45 −0
Original line number Diff line number Diff line
@@ -168,6 +168,13 @@ 
		ti,timers = <&timer11>;

		#pwm-cells = <3>;

	};



	/* HS USB Host PHY on PORT 1 */

	hsusb1_phy: hsusb1_phy {

		compatible = "usb-nop-xceiv";

		reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */

		#phy-cells = <0>;

	};

};



&davinci_emac {
@@ -224,7 +231,17 @@ 
      status = "disabled";

};



&usbhshost {

	port1-mode = "ehci-phy";

};



&usbhsehci {

	phys = <&hsusb1_phy>;

};



&omap3_pmx_core {

	pinctrl-names = "default";

	pinctrl-0 = <&hsusb1_rst_pins>;



	leds_pins: pinmux_leds_pins {

		pinctrl-single,pins = <
@@ -283,4 +300,32 @@ 
			OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)       /* dss_data15.dss_data15 */

		>;

	};



	hsusb1_rst_pins: pinmux_hsusb1_rst_pins {

		pinctrl-single,pins = <

			OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4)	/* gpmc_ncs6.gpio_57 */

		>;

	};

};



&omap3_pmx_core2 {

	pinctrl-names = "default";

	pinctrl-0 = <&hsusb1_pins>;



	hsusb1_pins: pinmux_hsusb1_pins {

		pinctrl-single,pins = <

			OMAP3430_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3)	/* etk_clk.hsusb1_stp */

			OMAP3430_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3)	/* etk_ctl.hsusb1_clk */

			OMAP3430_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3)	/* etk_d8.hsusb1_dir */

			OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3)	/* etk_d9.hsusb1_nxt */

			OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3)	/* etk_d0.hsusb1_data0 */

			OMAP3430_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3)	/* etk_d1.hsusb1_data1 */

			OMAP3430_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3)	/* etk_d2.hsusb1_data2 */

			OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3)	/* etk_d7.hsusb1_data3 */

			OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3)	/* etk_d4.hsusb1_data4 */

			OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3)	/* etk_d5.hsusb1_data5 */

			OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3)	/* etk_d6.hsusb1_data6 */

			OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3)	/* etk_d3.hsusb1_data7 */

		>;

	};

};