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Commit 5bbed0b3 authored by Piorkowski, Piotr's avatar Piorkowski, Piotr Committed by Chris Wilson
Browse files

drm/i915/guc: Remove GUC_CTL_DEVICE_INFO parameter 



It looks that GuC does not actively use GUC_CTL_DEVICE_INFO parameter
where we are passing GT type and Core family values.
Let's stop/remove setup of this parameter and remove related
definitions.

v2: (this time without squashed HAX)
  - New title and description
  - Remove also GUC_CORE_FAMILY_* definitions (Michel)
v3:
  - The removed define GUC_CTL_DEVICE_INFO has been restored (Michel)
  - Updated description (Sagar)
v4: rebase

Signed-off-by: default avatarPiotr Piórkowski <piotr.piorkowski@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: John A Spotswood <john.a.spotswood@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michel Thierry <michel.thierry@intel.com>
Acked-by: default avatarMichel Thierry <michel.thierry@intel.com>
Reviewed-by: default avatarSagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180413085245.57206-1-piotr.piorkowski@intel.com
parent fadec6ee

drivers/gpu/drm/i915/intel_guc.c

+0 −24
Original line number Diff line number Diff line
@@ -203,26 +203,6 @@ void intel_guc_fini(struct intel_guc *guc) 
	guc_shared_data_destroy(guc);

}



static u32 get_gt_type(struct drm_i915_private *dev_priv)

{

	/* XXX: GT type based on PCI device ID? field seems unused by fw */

	return 0;

}



static u32 get_core_family(struct drm_i915_private *dev_priv)

{

	u32 gen = INTEL_GEN(dev_priv);



	switch (gen) {

	case 9:

		return GUC_CORE_FAMILY_GEN9;



	default:

		MISSING_CASE(gen);

		return GUC_CORE_FAMILY_UNKNOWN;

	}

}



static u32 get_log_control_flags(void)

{

	u32 level = i915_modparams.guc_log_level;
@@ -255,10 +235,6 @@ void intel_guc_init_params(struct intel_guc *guc) 


	memset(params, 0, sizeof(params));



	params[GUC_CTL_DEVICE_INFO] |=

		(get_gt_type(dev_priv) << GUC_CTL_GT_TYPE_SHIFT) |

		(get_core_family(dev_priv) << GUC_CTL_CORE_FAMILY_SHIFT);



	/*

	 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one

	 * second. This ARAR is calculated by:

drivers/gpu/drm/i915/intel_guc_fwif.h

+0 −5
Original line number Diff line number Diff line
@@ -23,9 +23,6 @@ 
#ifndef _INTEL_GUC_FWIF_H

#define _INTEL_GUC_FWIF_H



#define GUC_CORE_FAMILY_GEN9		12

#define GUC_CORE_FAMILY_UNKNOWN		0x7fffffff



#define GUC_CLIENT_PRIORITY_KMD_HIGH	0

#define GUC_CLIENT_PRIORITY_HIGH	1

#define GUC_CLIENT_PRIORITY_KMD_NORMAL	2
@@ -82,8 +79,6 @@ 
#define GUC_CTL_ARAT_LOW		2



#define GUC_CTL_DEVICE_INFO		3

#define   GUC_CTL_GT_TYPE_SHIFT		0

#define   GUC_CTL_CORE_FAMILY_SHIFT	7



#define GUC_CTL_LOG_PARAMS		4

#define   GUC_LOG_VALID			(1 << 0)