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Commit 5b2adf89 authored by Jesse Barnes's avatar Jesse Barnes Committed by Chris Wilson
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drm/i915: add Ironlake clock gating workaround for FDI link training 



Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 9f0e7ff4

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -2782,6 +2782,7 @@ 
#define FDI_RXA_CHICKEN         0xc200c

#define FDI_RXA_CHICKEN         0xc200c

#define FDI_RXB_CHICKEN         0xc2010

#define FDI_RXB_CHICKEN         0xc2010

#define  FDI_RX_PHASE_SYNC_POINTER_ENABLE       (1)

#define  FDI_RX_PHASE_SYNC_POINTER_ENABLE       (1)

#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, FDI_RXA_CHICKEN, FDI_RXB_CHICKEN)





/* CPU: FDI_TX */

/* CPU: FDI_TX */

#define FDI_TXA_CTL             0x60100

#define FDI_TXA_CTL             0x60100

drivers/gpu/drm/i915/intel_display.c

+8 −0
Original line number Original line Diff line number Diff line
@@ -1714,6 +1714,9 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc) 
	POSTING_READ(reg);

	POSTING_READ(reg);

	udelay(150);

	udelay(150);





	/* Ironlake workaround, enable clock pointer after FDI enable*/

	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);



	reg = FDI_RX_IIR(pipe);

	reg = FDI_RX_IIR(pipe);

	for (tries = 0; tries < 5; tries++) {

	for (tries = 0; tries < 5; tries++) {

		temp = I915_READ(reg);

		temp = I915_READ(reg);
@@ -2192,6 +2195,11 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) 
	POSTING_READ(reg);

	POSTING_READ(reg);

	udelay(100);

	udelay(100);





	/* Ironlake workaround, disable clock pointer after downing FDI */

	I915_WRITE(FDI_RX_CHICKEN(pipe),

		   I915_READ(FDI_RX_CHICKEN(pipe) &

			     ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));



	/* still set train pattern 1 */

	/* still set train pattern 1 */

	reg = FDI_TX_CTL(pipe);

	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	temp = I915_READ(reg);