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Commit 5b1f3dc9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq updates from Thomas Gleixner:
 "The usual pile of boring changes:

   - Consolidate tasklet functions to share code instead of duplicating
     it

   - The first step for making the low level entry handler management on
     multi-platform kernels generic

   - A new sysfs file which allows to retrieve the wakeup state of
     interrupts.

   - Ensure that the interrupt thread follows the effective affinity and
     not the programmed affinity to avoid cross core wakeups.

   - Two new interrupt controller drivers (Microsemi Ocelot and Qualcomm
     PDC)

   - Fix the wakeup path clock handling for Reneasas interrupt chips.

   - Rework the boot time register reset for ARM GIC-V2/3

   - Better suspend/resume support for ARM GIV-V3/ITS

   - Add missing locking to the ARM GIC set_type() callback

   - Small fixes for the irq simulator code

   - SPDX identifiers for the irq core code and removal of boiler plate

   - Small cleanups all over the place"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (37 commits)
  openrisc: Set CONFIG_MULTI_IRQ_HANDLER
  arm64: Set CONFIG_MULTI_IRQ_HANDLER
  genirq: Make GENERIC_IRQ_MULTI_HANDLER depend on !MULTI_IRQ_HANDLER
  irqchip/gic: Take lock when updating irq type
  irqchip/gic: Update supports_deactivate static key to modern api
  irqchip/gic-v3: Ensure GICR_CTLR.EnableLPI=0 is observed before enabling
  irqchip: Add a driver for the Microsemi Ocelot controller
  dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller
  irqchip/gic-v3: Probe for SCR_EL3 being clear before resetting AP0Rn
  irqchip/gic-v3: Don't try to reset AP0Rn
  irqchip/gic-v3: Do not check trigger configuration of partitionned LPIs
  genirq: Remove license boilerplate/references
  genirq: Add missing SPDX identifiers
  genirq/matrix: Cleanup SPDX identifier
  genirq: Cleanup top of file comments
  genirq: Pass desc to __irq_free instead of irq number
  irqchip/gic-v3: Loudly complain about the use of IRQ_TYPE_NONE
  irqchip/gic: Loudly complain about the use of IRQ_TYPE_NONE
  RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler
  genirq: Add CONFIG_GENERIC_IRQ_MULTI_HANDLER
  ...
parents 680014d6 83fbdf1c

Documentation/ABI/testing/sysfs-kernel-irq

+7 −0
Original line number Diff line number Diff line
@@ -51,3 +51,10 @@ Date: September 2016 
KernelVersion:	4.9

Contact:	Craig Gallek <kraig@google.com>

Description:	The type of the interrupt.  Either the string 'level' or 'edge'.



What:		/sys/kernel/irq/<irq>/wakeup

Date:		March 2018

KernelVersion:	4.17

Contact:	Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Description:	The wakeup state of the interrupt. Either the string

		'enabled' or 'disabled'.

Documentation/admin-guide/kernel-parameters.txt

+8 −0
Original line number Diff line number Diff line
@@ -1739,6 +1739,14 @@ 
			of a GICv2 controller even if the memory range

			exposed by the device tree is too small.



	irqchip.gicv3_nolpi=

			[ARM, ARM64]

			Force the kernel to ignore the availability of

			LPIs (and by consequence ITSs). Intended for system

			that use the kernel as a bootloader, and thus want

			to let secondary kernels in charge of setting up

			LPIs.



	irqfixup	[HW]

			When an interrupt is not handled search all handlers

			for it. Intended to get systems with badly broken

Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt

0 → 100644
+22 −0
Original line number Diff line number Diff line 
Microsemi Ocelot SoC ICPU Interrupt Controller



Required properties:



- compatible : should be "mscc,ocelot-icpu-intr"

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The value shall be 1.

- interrupt-parent : phandle of the CPU interrupt controller.

- interrupts : Specifies the CPU interrupt the controller is connected to.



Example:



		intc: interrupt-controller@70000070 {

			compatible = "mscc,ocelot-icpu-intr";

			reg = <0x70000070 0x70>;

			#interrupt-cells = <1>;

			interrupt-controller;

			interrupt-parent = <&cpuintc>;

			interrupts = <2>;

		};

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt

0 → 100644
+78 −0
Original line number Diff line number Diff line 
PDC interrupt controller



Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a

Power Domain Controller (PDC) that is on always-on domain. In addition to

providing power control for the power domains, the hardware also has an

interrupt controller that can be used to help detect edge low interrupts as

well detect interrupts when the GIC is non-operational.



GIC is parent interrupt controller at the highest level. Platform interrupt

controller PDC is next in hierarchy, followed by others. Drivers requiring

wakeup capabilities of their device interrupts routed through the PDC, must

specify PDC as their interrupt controller and request the PDC port associated

with the GIC interrupt. See example below.



Properties:



- compatible:

	Usage: required

	Value type: <string>

	Definition: Should contain "qcom,<soc>-pdc"

		    - "qcom,sdm845-pdc": For SDM845



- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: Specifies the base physical address for PDC hardware.



- interrupt-cells:

	Usage: required

	Value type: <u32>

	Definition: Specifies the number of cells needed to encode an interrupt

		    source.

		    Must be 2.

		    The first element of the tuple is the PDC pin for the

		    interrupt.

		    The second element is the trigger type.



- interrupt-parent:

	Usage: required

	Value type: <phandle>

	Definition: Specifies the interrupt parent necessary for hierarchical

		    domain to operate.



- interrupt-controller:

	Usage: required

	Value type: <bool>

	Definition: Identifies the node as an interrupt controller.



- qcom,pdc-ranges:

	Usage: required

	Value type: <u32 array>

	Definition: Specifies the PDC pin offset and the number of PDC ports.

		    The tuples indicates the valid mapping of valid PDC ports

		    and their hwirq mapping.

		    The first element of the tuple is the starting PDC port.

		    The second element is the GIC hwirq number for the PDC port.

		    The third element is the number of interrupts in sequence.



Example:



	pdc: interrupt-controller@b220000 {

		compatible = "qcom,sdm845-pdc";

		reg = <0xb220000 0x30000>;

		qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;

		#interrupt-cells = <2>;

		interrupt-parent = <&intc>;

		interrupt-controller;

	};



DT binding of a device that wants to use the GIC SPI 514 as a wakeup

interrupt, must do -



	wake-device {

		interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;

	};



In this case interrupt 514 would be mapped to port 2 on the PDC as defined by

the qcom,pdc-ranges property.

arch/arm/include/asm/arch_gicv3.h

+32 −15
Original line number Diff line number Diff line
@@ -35,6 +35,18 @@ 
#define ICC_IGRPEN1			__ACCESS_CP15(c12, 0, c12, 7)

#define ICC_BPR1			__ACCESS_CP15(c12, 0, c12, 3)



#define __ICC_AP0Rx(x)			__ACCESS_CP15(c12, 0, c8, 4 | x)

#define ICC_AP0R0			__ICC_AP0Rx(0)

#define ICC_AP0R1			__ICC_AP0Rx(1)

#define ICC_AP0R2			__ICC_AP0Rx(2)

#define ICC_AP0R3			__ICC_AP0Rx(3)



#define __ICC_AP1Rx(x)			__ACCESS_CP15(c12, 0, c9, x)

#define ICC_AP1R0			__ICC_AP1Rx(0)

#define ICC_AP1R1			__ICC_AP1Rx(1)

#define ICC_AP1R2			__ICC_AP1Rx(2)

#define ICC_AP1R3			__ICC_AP1Rx(3)



#define ICC_HSRE			__ACCESS_CP15(c12, 4, c9, 5)



#define ICH_VSEIR			__ACCESS_CP15(c12, 4, c9, 4)
@@ -86,17 +98,17 @@ 
#define ICH_LRC14			__LRC8(6)

#define ICH_LRC15			__LRC8(7)



#define __AP0Rx(x)			__ACCESS_CP15(c12, 4, c8, x)

#define ICH_AP0R0			__AP0Rx(0)

#define ICH_AP0R1			__AP0Rx(1)

#define ICH_AP0R2			__AP0Rx(2)

#define ICH_AP0R3			__AP0Rx(3)

#define __ICH_AP0Rx(x)			__ACCESS_CP15(c12, 4, c8, x)

#define ICH_AP0R0			__ICH_AP0Rx(0)

#define ICH_AP0R1			__ICH_AP0Rx(1)

#define ICH_AP0R2			__ICH_AP0Rx(2)

#define ICH_AP0R3			__ICH_AP0Rx(3)



#define __AP1Rx(x)			__ACCESS_CP15(c12, 4, c9, x)

#define ICH_AP1R0			__AP1Rx(0)

#define ICH_AP1R1			__AP1Rx(1)

#define ICH_AP1R2			__AP1Rx(2)

#define ICH_AP1R3			__AP1Rx(3)

#define __ICH_AP1Rx(x)			__ACCESS_CP15(c12, 4, c9, x)

#define ICH_AP1R0			__ICH_AP1Rx(0)

#define ICH_AP1R1			__ICH_AP1Rx(1)

#define ICH_AP1R2			__ICH_AP1Rx(2)

#define ICH_AP1R3			__ICH_AP1Rx(3)



/* A32-to-A64 mappings used by VGIC save/restore */
@@ -125,6 +137,16 @@ static inline u64 read_ ## a64(void) \ 
	return val; 				\

}



CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)

CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1)

CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1)

CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1)

CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1)

CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1)

CPUIF_MAP(ICC_AP1R1, ICC_AP1R1_EL1)

CPUIF_MAP(ICC_AP1R2, ICC_AP1R2_EL1)

CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1)



CPUIF_MAP(ICH_HCR, ICH_HCR_EL2)

CPUIF_MAP(ICH_VTR, ICH_VTR_EL2)

CPUIF_MAP(ICH_MISR, ICH_MISR_EL2)
@@ -185,11 +207,6 @@ static inline u32 gic_read_iar(void) 
	return irqstat;

}



static inline void gic_write_pmr(u32 val)

{

	write_sysreg(val, ICC_PMR);

}



static inline void gic_write_ctlr(u32 val)

{

	write_sysreg(val, ICC_CTLR);