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Commit 5ab3d9d6 authored by Russell King's avatar Russell King Committed by Greg Kroah-Hartman
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ARM: uaccess: integrate uaccess_save and uaccess_restore



[ Upstream commit 8ede890b0bcebe8c760aacfe20e934d98c3dc6aa ]

Integrate uaccess_save / uaccess_restore macros into the new
uaccess_entry / uaccess_exit macros respectively.

Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent abd641e9
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+13 −17
Original line number Original line Diff line number Diff line
@@ -67,30 +67,23 @@
#endif
#endif
	.endm
	.endm


	.macro	uaccess_save, tmp
#ifdef CONFIG_CPU_SW_DOMAIN_PAN
#ifdef CONFIG_CPU_SW_DOMAIN_PAN
	mrc	p15, 0, \tmp, c3, c0, 0
#define DACR(x...)	x
	str	\tmp, [sp, #SVC_DACR]
#else
#endif
#define DACR(x...)
	.endm

	.macro	uaccess_restore
#ifdef CONFIG_CPU_SW_DOMAIN_PAN
	ldr	r0, [sp, #SVC_DACR]
	mcr	p15, 0, r0, c3, c0, 0
#endif
#endif
	.endm


	/*
	/*
	 * Save the address limit on entry to a privileged exception and
	 * Save the address limit on entry to a privileged exception and
	 * if using PAN, save and disable usermode access.
	 * if using PAN, save and disable usermode access.
	 */
	 */
	.macro	uaccess_entry, tsk, tmp0, tmp1, tmp2, disable
	.macro	uaccess_entry, tsk, tmp0, tmp1, tmp2, disable
	ldr	\tmp0, [\tsk, #TI_ADDR_LIMIT]
	ldr	\tmp1, [\tsk, #TI_ADDR_LIMIT]
	mov	\tmp1, #TASK_SIZE
	mov	\tmp2, #TASK_SIZE
	str	\tmp1, [\tsk, #TI_ADDR_LIMIT]
	str	\tmp2, [\tsk, #TI_ADDR_LIMIT]
	str	\tmp0, [sp, #SVC_ADDR_LIMIT]
 DACR(	mrc	p15, 0, \tmp0, c3, c0, 0)
	uaccess_save \tmp0
 DACR(	str	\tmp0, [sp, #SVC_DACR])
	str	\tmp1, [sp, #SVC_ADDR_LIMIT]
	.if \disable
	.if \disable
	uaccess_disable \tmp0
	uaccess_disable \tmp0
	.endif
	.endif
@@ -99,8 +92,11 @@
	/* Restore the user access state previously saved by uaccess_entry */
	/* Restore the user access state previously saved by uaccess_entry */
	.macro	uaccess_exit, tsk, tmp0, tmp1
	.macro	uaccess_exit, tsk, tmp0, tmp1
	ldr	\tmp1, [sp, #SVC_ADDR_LIMIT]
	ldr	\tmp1, [sp, #SVC_ADDR_LIMIT]
	uaccess_restore
 DACR(	ldr	\tmp0, [sp, #SVC_DACR])
	str	\tmp1, [\tsk, #TI_ADDR_LIMIT]
	str	\tmp1, [\tsk, #TI_ADDR_LIMIT]
 DACR(	mcr	p15, 0, \tmp0, c3, c0, 0)
	.endm
	.endm


#undef DACR

#endif /* __ASM_UACCESS_ASM_H__ */
#endif /* __ASM_UACCESS_ASM_H__ */