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Commit 5a7bfded authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
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drm/amd/amdgpu: gfx6 tidy up raster config 



Clean up coding style in gfx_v6_0_write_harvested_raster_configs()

Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 167327d6

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

+8 −12
Original line number Diff line number Diff line
@@ -1195,24 +1195,22 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, 
		if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {

			raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;



			if (!se_mask[idx]) {

			if (!se_mask[idx])

				raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;

			} else {

			else

				raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;

		}

		}



		pkr0_mask &= rb_mask;

		pkr1_mask &= rb_mask;

		if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {

			raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;



			if (!pkr0_mask) {

			if (!pkr0_mask)

				raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;

			} else {

			else

				raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;

		}

		}



		if (rb_per_se >= 2) {

			unsigned rb0_mask = 1 << (se * rb_per_se);
@@ -1223,14 +1221,13 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, 
			if (!rb0_mask || !rb1_mask) {

				raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;



				if (!rb0_mask) {

				if (!rb0_mask)

					raster_config_se |=

						RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;

				} else {

				else

					raster_config_se |=

						RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;

			}

			}



			if (rb_per_se > 2) {

				rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
@@ -1240,16 +1237,15 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, 
				if (!rb0_mask || !rb1_mask) {

					raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;



					if (!rb0_mask) {

					if (!rb0_mask)

						raster_config_se |=

							RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;

					} else {

					else

						raster_config_se |=

							RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;

				}

			}

		}

		}



		/* GRBM_GFX_INDEX has a different offset on SI */

		gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);