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Commit 5a7862e8 authored by Will Deacon's avatar Will Deacon Committed by Catalin Marinas
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arm64: tlbflush: avoid flushing when fullmm == 1 



The TLB gather code sets fullmm=1 when tearing down the entire address
space for an mm_struct on exit or execve. Given that the ASID allocator
will never re-allocate a dirty ASID, this flushing is not needed and can
simply be avoided in the flushing code.

Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent f3e002c2

arch/arm64/include/asm/tlb.h

+15 −11
Original line number Diff line number Diff line
@@ -37,10 +37,15 @@ static inline void __tlb_remove_table(void *_table) 


static inline void tlb_flush(struct mmu_gather *tlb)

{

	if (tlb->fullmm) {

		flush_tlb_mm(tlb->mm);

	} else {

	struct vm_area_struct vma = { .vm_mm = tlb->mm, };



	/*

	 * The ASID allocator will either invalidate the ASID or mark

	 * it as used.

	 */

	if (tlb->fullmm)

		return;



	/*

	 * The intermediate page table levels are already handled by

	 * the __(pte|pmd|pud)_free_tlb() functions, so last level
@@ -48,7 +53,6 @@ static inline void tlb_flush(struct mmu_gather *tlb) 
	 */

	__flush_tlb_range(&vma, tlb->start, tlb->end, true);

}

}



static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,

				  unsigned long addr)