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Commit 5a3f25db authored by Junwei Zhang's avatar Junwei Zhang Committed by Alex Deucher
Browse files

drm/amdgpu/dce8: fix flash with white screen on monitor 



Fixed mc stop and resume hardware programming sequence.

Signed-off-by: default avatarJunwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9ecbe7f5

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

+7 −60
Original line number Diff line number Diff line
@@ -526,36 +526,16 @@ static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev, 
		crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),

					     CRTC_CONTROL, CRTC_MASTER_EN);

		if (crtc_enabled) {

#if 0

			u32 frame_count;

			int j;



#if 1

			save->crtc_enabled[i] = true;

			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);

			if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {

				amdgpu_display_vblank_wait(adev, i);

				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);

				/*it is correct only for RGB ; black is 0*/

				WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);

				tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);

				WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);

				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);

			}

			/* wait for the next frame */

			frame_count = amdgpu_display_vblank_get_counter(adev, i);

			for (j = 0; j < adev->usec_timeout; j++) {

				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)

					break;

				udelay(1);

			}

			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);

			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {

				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);

				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);

			}

			tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);

			if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {

				tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);

				WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);

			}

			mdelay(20);

#else

			/* XXX this is a hack to avoid strange behavior with EFI on certain systems */

			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
@@ -575,55 +555,22 @@ static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev, 
static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,

				      struct amdgpu_mode_mc_save *save)

{

	u32 tmp, frame_count;

	int i, j;

	u32 tmp;

	int i;



	/* update crtc base addresses */

	for (i = 0; i < adev->mode_info.num_crtc; i++) {

		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],

		       upper_32_bits(adev->mc.vram_start));

		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],

		       upper_32_bits(adev->mc.vram_start));

		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],

		       (u32)adev->mc.vram_start);

		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],

		       (u32)adev->mc.vram_start);



		if (save->crtc_enabled[i]) {

			tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);

			if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {

				tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);

				WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);

			}

			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);

			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {

				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);

				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);

			}

			tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);

			if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {

				tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);

				WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);

			}

			for (j = 0; j < adev->usec_timeout; j++) {

				tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);

				if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)

					break;

				udelay(1);

			}

			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);

			tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);

			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);

			WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);

			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);

			/* wait for the next frame */

			frame_count = amdgpu_display_vblank_get_counter(adev, i);

			for (j = 0; j < adev->usec_timeout; j++) {

				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)

					break;

				udelay(1);

			}

		}

		mdelay(20);

	}



	WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));