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Commit 598fac6b authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: magic VLV PLL registers in the dpio sideband 



Stolen from a patch with the below impressive sob-section.

Signed-off-by: default avatarPallavi G <pallavi.g@intel.com>
Signed-off-by: default avatarVijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: default avatarGajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: default avatarBen Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Drop everything but the header #defines.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 75e53986

drivers/gpu/drm/i915/i915_reg.h

+116 −2
Original line number Diff line number Diff line
@@ -353,6 +353,8 @@ 
 *  0x8100: fast clock controls

 *

 * DPIO is VLV only.

 *

 * Note: digital port B is DDI0, digital pot C is DDI1

 */

#define DPIO_PKT			(VLV_DISPLAY_BASE + 0x2100)

#define  DPIO_RID			(0<<24)
@@ -369,8 +371,20 @@ 
#define  DPIO_SFR_BYPASS		(1<<1)

#define  DPIO_RESET			(1<<0)



#define _DPIO_TX3_SWING_CTL4_A		0x690

#define _DPIO_TX3_SWING_CTL4_B		0x2a90

#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL4_A, \

					_DPIO_TX3_SWING_CTL4_B)



/*

 * Per pipe/PLL DPIO regs

 */

#define _DPIO_DIV_A			0x800c

#define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */

#define   DPIO_POST_DIV_DAC		0

#define   DPIO_POST_DIV_HDMIDP		1 /* DAC 225-400M rate */

#define   DPIO_POST_DIV_LVDS1		2

#define   DPIO_POST_DIV_LVDS2		3

#define   DPIO_K_SHIFT			(24) /* 4 bits */

#define   DPIO_P1_SHIFT			(21) /* 3 bits */

#define   DPIO_P2_SHIFT			(16) /* 5 bits */
@@ -396,12 +410,109 @@ 
#define _DPIO_CORE_CLK_B		0x803c

#define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)



#define _DPIO_IREF_CTL_A		0x8040

#define _DPIO_IREF_CTL_B		0x8060

#define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B)



#define DPIO_IREF_BCAST			0xc044

#define _DPIO_IREF_A			0x8044

#define _DPIO_IREF_B			0x8064

#define DPIO_IREF(pipe) _PIPE(pipe, _DPIO_IREF_A, _DPIO_IREF_B)



#define _DPIO_PLL_CML_A			0x804c

#define _DPIO_PLL_CML_B			0x806c

#define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B)



#define _DPIO_LFP_COEFF_A		0x8048

#define _DPIO_LFP_COEFF_B		0x8068

#define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B)



#define DPIO_CALIBRATION		0x80ac



#define DPIO_FASTCLK_DISABLE		0x8100



/*

 * Per DDI channel DPIO regs

 */



#define _DPIO_PCS_TX_0			0x8200

#define _DPIO_PCS_TX_1			0x8400

#define   DPIO_PCS_TX_LANE2_RESET	(1<<16)

#define   DPIO_PCS_TX_LANE1_RESET	(1<<7)

#define DPIO_PCS_TX(port) _PORT(port, _DPIO_PCS_TX_0, _DPIO_PCS_TX_1)



#define _DPIO_PCS_CLK_0			0x8204

#define _DPIO_PCS_CLK_1			0x8404

#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1<<22)

#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)

#define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)

#define   DPIO_PCS_CLK_SOFT_RESET	(1<<5)

#define DPIO_PCS_CLK(port) _PORT(port, _DPIO_PCS_CLK_0, _DPIO_PCS_CLK_1)



#define _DPIO_PCS_CTL_OVR1_A		0x8224

#define _DPIO_PCS_CTL_OVR1_B		0x8424

#define DPIO_PCS_CTL_OVER1(port) _PORT(port, _DPIO_PCS_CTL_OVR1_A, \

				       _DPIO_PCS_CTL_OVR1_B)



#define _DPIO_PCS_STAGGER0_A		0x822c

#define _DPIO_PCS_STAGGER0_B		0x842c

#define DPIO_PCS_STAGGER0(port) _PORT(port, _DPIO_PCS_STAGGER0_A, \

				      _DPIO_PCS_STAGGER0_B)



#define _DPIO_PCS_STAGGER1_A		0x8230

#define _DPIO_PCS_STAGGER1_B		0x8430

#define DPIO_PCS_STAGGER1(port) _PORT(port, _DPIO_PCS_STAGGER1_A, \

				      _DPIO_PCS_STAGGER1_B)



#define _DPIO_PCS_CLOCKBUF0_A		0x8238

#define _DPIO_PCS_CLOCKBUF0_B		0x8438

#define DPIO_PCS_CLOCKBUF0(port) _PORT(port, _DPIO_PCS_CLOCKBUF0_A, \

				       _DPIO_PCS_CLOCKBUF0_B)



#define _DPIO_PCS_CLOCKBUF8_A		0x825c

#define _DPIO_PCS_CLOCKBUF8_B		0x845c

#define DPIO_PCS_CLOCKBUF8(port) _PORT(port, _DPIO_PCS_CLOCKBUF8_A, \

				       _DPIO_PCS_CLOCKBUF8_B)



#define _DPIO_TX_SWING_CTL2_A		0x8288

#define _DPIO_TX_SWING_CTL2_B		0x8488

#define DPIO_TX_SWING_CTL2(port) _PORT(port, _DPIO_TX_SWING_CTL2_A, \

				       _DPIO_TX_SWING_CTL2_B)



#define _DPIO_TX_SWING_CTL3_A		0x828c

#define _DPIO_TX_SWING_CTL3_B		0x848c

#define DPIO_TX_SWING_CTL3(port) _PORT(port, _DPIO_TX_SWING_CTL3_A, \

				       _DPIO_TX_SWING_CTL3_B)



#define _DPIO_TX_SWING_CTL4_A		0x8290

#define _DPIO_TX_SWING_CTL4_B		0x8490

#define DPIO_TX_SWING_CTL4(port) _PORT(port, _DPIO_TX_SWING_CTL4_A, \

				       _DPIO_TX_SWING_CTL4_B)



#define _DPIO_TX_OCALINIT_0		0x8294

#define _DPIO_TX_OCALINIT_1		0x8494

#define   DPIO_TX_OCALINIT_EN		(1<<31)

#define DPIO_TX_OCALINIT(port) _PORT(port, _DPIO_TX_OCALINIT_0, \

				     _DPIO_TX_OCALINIT_1)



#define _DPIO_TX_CTL_0			0x82ac

#define _DPIO_TX_CTL_1			0x84ac

#define DPIO_TX_CTL(port) _PORT(port, _DPIO_TX_CTL_0, _DPIO_TX_CTL_1)



#define _DPIO_TX_LANE_0			0x82b8

#define _DPIO_TX_LANE_1			0x84b8

#define DPIO_TX_LANE(port) _PORT(port, _DPIO_TX_LANE_0, _DPIO_TX_LANE_1)



#define _DPIO_DATA_CHANNEL1		0x8220

#define _DPIO_DATA_CHANNEL2		0x8420

#define DPIO_DATA_CHANNEL(port) _PORT(port, _DPIO_DATA_CHANNEL1, _DPIO_DATA_CHANNEL2)



#define _DPIO_PORT0_PCS0		0x0220

#define _DPIO_PORT0_PCS1		0x0420

#define _DPIO_PORT1_PCS2		0x2620

#define _DPIO_PORT1_PCS3		0x2820

#define DPIO_DATA_LANE_A(port) _PORT(port, _DPIO_PORT0_PCS0, _DPIO_PORT1_PCS2)

#define DPIO_DATA_LANE_B(port) _PORT(port, _DPIO_PORT0_PCS1, _DPIO_PORT1_PCS3)

#define DPIO_DATA_CHANNEL1              0x8220

#define DPIO_DATA_CHANNEL2              0x8420
@@ -965,7 +1076,10 @@ 
#define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */

#define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */

#define   DPLL_LOCK_VLV			(1<<15)

#define   DPLL_INTEGRATED_CRI_CLK_VLV	(1<<14)

#define   DPLL_INTEGRATED_CLOCK_VLV	(1<<13)

#define   DPLL_PORTC_READY_MASK		(0xf << 4)

#define   DPLL_PORTB_READY_MASK		(0xf)



#define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000

/*