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Commit 59858a1c authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "usb: dwc3: Add tuning support for Gen2 Tx compliance parameters"

parents 9a819aea 9ca4ee13

drivers/usb/dwc3/core.c

+29 −0
Original line number Diff line number Diff line
@@ -1069,6 +1069,19 @@ int dwc3_core_init(struct dwc3 *dwc) 
		dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);

	}



	if (dwc->gen2_tx_de_emph != -1)

		dwc3_writel(dwc->regs, DWC31_LCSR_TX_DEEMPH(0),

			dwc->gen2_tx_de_emph & DWC31_TX_DEEMPH_MASK);

	if (dwc->gen2_tx_de_emph1 != -1)

		dwc3_writel(dwc->regs, DWC31_LCSR_TX_DEEMPH_1(0),

			dwc->gen2_tx_de_emph1 & DWC31_TX_DEEMPH_MASK);

	if (dwc->gen2_tx_de_emph2 != -1)

		dwc3_writel(dwc->regs, DWC31_LCSR_TX_DEEMPH_2(0),

			dwc->gen2_tx_de_emph2 & DWC31_TX_DEEMPH_MASK);

	if (dwc->gen2_tx_de_emph3 != -1)

		dwc3_writel(dwc->regs, DWC31_LCSR_TX_DEEMPH_3(0),

			dwc->gen2_tx_de_emph3 & DWC31_TX_DEEMPH_MASK);



	dwc3_notify_event(dwc, DWC3_CONTROLLER_POST_RESET_EVENT, 0);



	/* set inter-packet gap 199.794ns to improve EL_23 margin */
@@ -1322,6 +1335,22 @@ static void dwc3_get_properties(struct dwc3 *dwc) 
	dwc->dis_metastability_quirk = device_property_read_bool(dev,

				"snps,dis_metastability_quirk");



	dwc->gen2_tx_de_emph = -1;

	device_property_read_u32(dev, "snps,gen2-tx-de-emph",

			&dwc->gen2_tx_de_emph);



	dwc->gen2_tx_de_emph1 = -1;

	device_property_read_u32(dev, "snps,gen2-tx-de-emph1",

			&dwc->gen2_tx_de_emph1);



	dwc->gen2_tx_de_emph2 = -1;

	device_property_read_u32(dev, "snps,gen2-tx-de-emph2",

			&dwc->gen2_tx_de_emph2);



	dwc->gen2_tx_de_emph3 = -1;

	device_property_read_u32(dev, "snps,gen2-tx-de-emph3",

			&dwc->gen2_tx_de_emph3);



	dwc->lpm_nyet_threshold = lpm_nyet_threshold;

	dwc->tx_de_emphasis = tx_de_emphasis;

drivers/usb/dwc3/core.h

+11 −0
Original line number Diff line number Diff line
@@ -171,6 +171,13 @@ 
#define GEN1_U3_EXIT_RSP_RX_CLK_MASK	GEN1_U3_EXIT_RSP_RX_CLK(0xff)

#define DWC31_LINK_GDBGLTSSM	0xd050



/* DWC 3.1 Tx De-emphasis Registers */

#define DWC31_LCSR_TX_DEEMPH(n)	(0xd060 + ((n) * 0x80))

#define DWC31_LCSR_TX_DEEMPH_1(n)	(0xd064 + ((n) * 0x80))

#define DWC31_LCSR_TX_DEEMPH_2(n)	(0xd068 + ((n) * 0x80))

#define DWC31_LCSR_TX_DEEMPH_3(n)	(0xd06c + ((n) * 0x80))

#define DWC31_TX_DEEMPH_MASK	0x3ffff



/* Bit fields */



/* Global SoC Bus Configuration Register 1 */
@@ -1348,6 +1355,10 @@ struct dwc3 { 
	int			retries_on_error;

	/*  If true, GDSC collapse will happen in HOST mode bus suspend */

	bool			gdsc_collapse_in_host_suspend;

	u32			gen2_tx_de_emph;

	u32			gen2_tx_de_emph1;

	u32			gen2_tx_de_emph2;

	u32			gen2_tx_de_emph3;

};



#define INCRX_BURST_MODE 0