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Commit 59069676 authored by Michael Hennerich's avatar Michael Hennerich Committed by Bryan Wu
Browse files

Blackfin arch: IO Port functions to read/write unalligned memory 



Signed-off-by: default avatarMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent 86ad7932

arch/blackfin/kernel/bfin_ksyms.c

+2 −0
Original line number Diff line number Diff line
@@ -90,7 +90,9 @@ EXPORT_SYMBOL(__umodsi3); 
EXPORT_SYMBOL(outsb);

EXPORT_SYMBOL(insb);

EXPORT_SYMBOL(outsw);

EXPORT_SYMBOL(outsw_8);

EXPORT_SYMBOL(insw);

EXPORT_SYMBOL(insw_8);

EXPORT_SYMBOL(outsl);

EXPORT_SYMBOL(insl);

EXPORT_SYMBOL(insl_16);

arch/blackfin/lib/ins.S

+18 −3
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ 
 * Description:  Implementation of ins{bwl} for BlackFin processors using zero overhead loops.

 *

 * Modified:

 *               Copyright 2004-2006 Analog Devices Inc.

 *               Copyright 2004-2008 Analog Devices Inc.

 *               Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>

 *

 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
@@ -63,6 +63,23 @@ ENTRY(_insw) 
	RTS;

ENDPROC(_insw)



ENTRY(_insw_8)

	P0 = R0;	/* P0 = port */

	cli R3;

	P1 = R1;	/* P1 = address */

	P2 = R2;	/* P2 = count */

	SSYNC;

	LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;

.Lword8_loop_s:  R0 = W[P0];

		B[P1++] = R0;

		R0 = R0 >> 8;

		B[P1++] = R0;

		NOP;

.Lword8_loop_e: NOP;

	sti R3;

	RTS;

ENDPROC(_insw_8)



ENTRY(_insb)

	P0 = R0;	/* P0 = port */

	cli R3;
@@ -78,8 +95,6 @@ ENTRY(_insb) 
	RTS;

ENDPROC(_insb)







ENTRY(_insl_16)

	P0 = R0;	/* P0 = port */

	cli R3;

arch/blackfin/lib/outs.S

+15 −1
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ 
 * Description:  Implementation of outs{bwl} for BlackFin processors using zero overhead loops.

 *

 * Modified:     Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>

 *               Copyright 2004-2006 Analog Devices Inc.

 *               Copyright 2004-2008 Analog Devices Inc.

 *

 * Bugs:         Enter bugs at http://blackfin.uclinux.org/

 *
@@ -63,3 +63,17 @@ ENTRY(_outsb) 
.Lbyte_loop_e: B[P0] = R0;

	RTS;

ENDPROC(_outsb)



ENTRY(_outsw_8)

	P0 = R0;	/* P0 = port */

	P1 = R1;	/* P1 = address */

	P2 = R2;	/* P2 = count */



	LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;

.Lword8_loop_s: R1 = B[P1++];

		R0 = B[P1++];

		R0 = R0 << 8;

		R0 = R0 + R1;

.Lword8_loop_e: W[P0] = R0;

	RTS;

ENDPROC(_outsw)

include/asm-blackfin/io.h

+2 −0
Original line number Diff line number Diff line
@@ -117,10 +117,12 @@ static inline unsigned int readl(const volatile void __iomem *addr) 


extern void outsb(unsigned long port, const void *addr, unsigned long count);

extern void outsw(unsigned long port, const void *addr, unsigned long count);

extern void outsw_8(unsigned long port, const void *addr, unsigned long count);

extern void outsl(unsigned long port, const void *addr, unsigned long count);



extern void insb(unsigned long port, void *addr, unsigned long count);

extern void insw(unsigned long port, void *addr, unsigned long count);

extern void insw_8(unsigned long port, void *addr, unsigned long count);

extern void insl(unsigned long port, void *addr, unsigned long count);

extern void insl_16(unsigned long port, void *addr, unsigned long count);