Commit 58fd1413 authored Jul 31, 2020 by Dinh Nguyen Committed by Greg Kroah-Hartman Sep 17, 2020

ARM: dts: socfpga: fix register entry for timer3 on Arria10



[ Upstream commit 0ff5a4812be4ebd4782bbb555d369636eea164f7 ]

Fixes the register address for the timer3 entry on Arria10.

Fixes: 475dc86d ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

parent a6c1919a

arch/arm/boot/dts/socfpga_arria10.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -791,7 +791,7 @@
		timer3: timer3@ffd00100 {
		compatible = "snps,dw-apb-timer";
		interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0xffd01000 0x100>;
		reg = <0xffd00100 0x100>;
		clocks = <&l4_sys_free_clk>;
		clock-names = "timer";
		};