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Commit 58c3f14f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-4.19-rc2' of... 

Merge tag 'riscv-for-linus-4.19-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux

Pull RISC-V fixes from Palmer Dabbelt:
 "RISC-V Fixes and Cleanups for 4.19-rc2

  This contains a handful of patches that filtered their way in during
  the merge window but just didn't make the deadline. It includes:

   - Additional documentation in the riscv,cpu-intc device tree binding
     that resulted from some feedback I missed in the original patch
     set.

   - A build fix that provides the definition of tlb_flush() before
     including tlb.h, which fixes a RISC-V build regression introduced
     during this merge window.

   - A cosmetic cleanup to sys_riscv_flush_icache()"

* tag 'riscv-for-linus-4.19-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux:
  RISC-V: Use a less ugly workaround for unused variable warnings
  riscv: tlb: Provide definition of tlb_flush() before including tlb.h
  dt-bindings: riscv,cpu-intc: Cleanups from a missed review
parents ff69279a 47d80a68

Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt

+11 −3
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ The RISC-V supervisor ISA manual specifies three interrupt sources that are 
attached to every HLIC: software interrupts, the timer interrupt, and external

interrupts.  Software interrupts are used to send IPIs between cores.  The

timer interrupt comes from an architecturally mandated real-time timer that is

controller via Supervisor Binary Interface (SBI) calls and CSR reads.  External

controlled via Supervisor Binary Interface (SBI) calls and CSR reads.  External

interrupts connect all other device interrupts to the HLIC, which are routed

via the platform-level interrupt controller (PLIC).
@@ -25,7 +25,15 @@ in the system. 


Required properties:

- compatible : "riscv,cpu-intc"

- #interrupt-cells : should be <1>

- #interrupt-cells : should be <1>.  The interrupt sources are defined by the

  RISC-V supervisor ISA manual, with only the following three interrupts being

  defined for supervisor mode:

    - Source 1 is the supervisor software interrupt, which can be sent by an SBI

      call and is reserved for use by software.

    - Source 5 is the supervisor timer interrupt, which can be configured by

      SBI calls and implements a one-shot timer.

    - Source 9 is the supervisor external interrupt, which chains to all other

      device interrupts.

- interrupt-controller : Identifies the node as an interrupt controller



Furthermore, this interrupt-controller MUST be embedded inside the cpu
@@ -38,7 +46,7 @@ An example device tree entry for a HLIC is show below. 
		...

		cpu1-intc: interrupt-controller {

			#interrupt-cells = <1>;

			compatible = "riscv,cpu-intc", "sifive,fu540-c000-cpu-intc";

			compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";

			interrupt-controller;

		};

	};

arch/riscv/include/asm/tlb.h

+4 −0
Original line number Diff line number Diff line
@@ -14,6 +14,10 @@ 
#ifndef _ASM_RISCV_TLB_H

#define _ASM_RISCV_TLB_H



struct mmu_gather;



static void tlb_flush(struct mmu_gather *tlb);



#include <asm-generic/tlb.h>



static inline void tlb_flush(struct mmu_gather *tlb)

arch/riscv/kernel/sys_riscv.c

+1 −14
Original line number Diff line number Diff line
@@ -65,24 +65,11 @@ SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len, 
SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end,

	uintptr_t, flags)

{

#ifdef CONFIG_SMP

	struct mm_struct *mm = current->mm;

	bool local = (flags & SYS_RISCV_FLUSH_ICACHE_LOCAL) != 0;

#endif



	/* Check the reserved flags. */

	if (unlikely(flags & ~SYS_RISCV_FLUSH_ICACHE_ALL))

		return -EINVAL;



	/*

	 * Without CONFIG_SMP flush_icache_mm is a just a flush_icache_all(),

	 * which generates unused variable warnings all over this function.

	 */

#ifdef CONFIG_SMP

	flush_icache_mm(mm, local);

#else

	flush_icache_all();

#endif

	flush_icache_mm(current->mm, flags & SYS_RISCV_FLUSH_ICACHE_LOCAL);



	return 0;

}