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Commit 58bdee70 authored by Vivek Aknurwar's avatar Vivek Aknurwar Committed by Gerrit - the friendly Code Review server
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clk: qcom: pll config updates 



pll config updates for cam cc, disp cc
gpu cc and video cc.

Change-Id: Iae515f15eefbf32203168d309b7ff5da2a811ec5
Signed-off-by: default avatarVivek Aknurwar <viveka@codeaurora.org>
parent 2f157693

drivers/clk/qcom/camcc-kona.c

+10 −9
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.*/

/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.*/



#define pr_fmt(fmt) "clk: %s: " fmt, __func__
@@ -181,7 +181,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = { 
	.alpha = 0x8000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00003100,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -257,7 +257,7 @@ static const struct alpha_pll_config cam_cc_pll1_config = { 
	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000100,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -326,7 +326,7 @@ static const struct alpha_pll_config cam_cc_pll2_config_sm8250_v2 = { 
	.cal_l = 0x4B,

	.alpha = 0x0,

	.config_ctl_val = 0x08200920,

	.config_ctl_hi_val = 0x05008011,

	.config_ctl_hi_val = 0x05002015,

	.config_ctl_hi1_val = 0x00000000,

	.user_ctl_val = 0x00000100,

	.user_ctl_hi_val = 0x00000000,
@@ -347,9 +347,9 @@ static struct clk_alpha_pll cam_cc_pll2 = { 
			.vdd_class = &vdd_mx,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {

				[VDD_LOWER] = 1600000000,

				[VDD_LOW] = 2000000000,

				[VDD_NOMINAL] = 2900000000,

				[VDD_LOWER] = 1800000000,

				[VDD_LOW] = 2400000000,

				[VDD_NOMINAL] = 3000000000,

				[VDD_HIGH] = 3600000000},

		},

	},
@@ -382,7 +382,7 @@ static const struct alpha_pll_config cam_cc_pll3_config = { 
	.alpha = 0x7555,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000100,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -437,7 +437,7 @@ static const struct alpha_pll_config cam_cc_pll4_config = { 
	.alpha = 0x7555,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000100,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -2803,6 +2803,7 @@ static int cam_cc_kona_probe(struct platform_device *pdev) 
	}



	dev_info(&pdev->dev, "Registered CAM CC clocks\n");



	return ret;

}

drivers/clk/qcom/dispcc-kona.c

+9 −9
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */

/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. */



#define pr_fmt(fmt) "clk: %s: " fmt, __func__
@@ -208,10 +208,11 @@ static struct pll_vco lucid_vco[] = { 


static const struct alpha_pll_config disp_cc_pll0_config = {

	.l = 0x47,

	.cal_l = 0x44,

	.alpha = 0xE000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -241,10 +242,11 @@ static struct clk_alpha_pll disp_cc_pll0 = { 


static const struct alpha_pll_config disp_cc_pll1_config = {

	.l = 0x1F,

	.cal_l = 0x44,

	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -481,8 +483,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = { 
		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 19200,

			[VDD_LOWER] = 162000,

			[VDD_LOW] = 270000,

			[VDD_LOWER] = 270000,

			[VDD_LOW_L1] = 540000,

			[VDD_NOMINAL] = 810000},

	},
@@ -504,8 +505,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { 
		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 19200,

			[VDD_LOWER] = 162000,

			[VDD_LOW] = 270000,

			[VDD_LOWER] = 270000,

			[VDD_LOW_L1] = 540000,

			[VDD_NOMINAL] = 810000},

	},
@@ -527,7 +527,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { 
		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 19200,

			[VDD_LOWER] = 337500,

			[VDD_LOW_L1] = 675000},

			[VDD_NOMINAL] = 675000},

	},

};
@@ -547,7 +547,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = { 
		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 19200,

			[VDD_LOWER] = 337500,

			[VDD_LOW_L1] = 675000},

			[VDD_NOMINAL] = 675000},

	},

};

drivers/clk/qcom/gpucc-kona.c

+74 −2
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.*/

/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.*/



#define pr_fmt(fmt) "clk: %s: " fmt, __func__
@@ -66,13 +66,59 @@ static struct pll_vco lucid_vco[] = { 
	{ 249600000, 2000000000, 0 },

};



static const struct alpha_pll_config gpu_cc_pll0_config = {

	.l = 0x13,

	.cal_l = 0x44,

	.alpha = 0xCAAA,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

};



static const struct alpha_pll_config gpu_cc_pll0_config_sm8250_v2 = {

	.l = 0x14,

	.cal_l = 0x44,

	.alpha = 0x5000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

};



static struct clk_alpha_pll gpu_cc_pll0 = {

	.offset = 0x0,

	.vco_table = lucid_vco,

	.num_vco = ARRAY_SIZE(lucid_vco),

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_pll0",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.ops = &clk_alpha_pll_lucid_ops,

			.vdd_class = &vdd_mx,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {

				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1600000000,

				[VDD_NOMINAL] = 2000000000},

		},

	},

};



static const struct alpha_pll_config gpu_cc_pll1_config = {

	.l = 0x1A,

	.cal_l = 0x44,

	.alpha = 0xAAA,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -398,10 +444,33 @@ static const struct qcom_cc_desc gpu_cc_kona_desc = { 


static const struct of_device_id gpu_cc_kona_match_table[] = {

	{ .compatible = "qcom,gpucc-kona" },

	{ .compatible = "qcom,gpucc-kona-v2" },

	{ }

};

MODULE_DEVICE_TABLE(of, gpu_cc_kona_match_table);



static void gpu_cc_kona_fixup_konav2(struct regmap *regmap)

{

	clk_lucid_pll_configure(&gpu_cc_pll0, regmap,

		&gpu_cc_pll0_config_sm8250_v2);

}



static int gpu_cc_kona_fixup(struct platform_device *pdev,

	struct regmap *regmap)

{

	const char *compat = NULL;

	int compatlen = 0;



	compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen);

	if (!compat || (compatlen <= 0))

		return -EINVAL;



	if (!strcmp(compat, "qcom,gpucc-kona-v2"))

		gpu_cc_kona_fixup_konav2(regmap);



	return 0;

}



static int gpu_cc_kona_probe(struct platform_device *pdev)

{

	struct regmap *regmap;
@@ -435,6 +504,9 @@ static int gpu_cc_kona_probe(struct platform_device *pdev) 
	value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;

	regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg,

							mask, value);

	ret = gpu_cc_kona_fixup(pdev, regmap);

	if (ret)

		return ret;



	ret = qcom_cc_really_probe(pdev, &gpu_cc_kona_desc, regmap);

	if (ret) {

drivers/clk/qcom/videocc-kona.c

+3 −3
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.*/

/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.*/



#define pr_fmt(fmt) "clk: %s: " fmt, __func__
@@ -126,7 +126,7 @@ static const struct alpha_pll_config video_pll0_config = { 
	.alpha = 0x8000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -160,7 +160,7 @@ static const struct alpha_pll_config video_pll1_config = { 
	.alpha = 0xFAAA,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x329A699C,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,