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Commit 58a86c45 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'mlx5-fixes' 



Saeed Mahameed says:

====================
Mellanox 100G mlx5 fixes 2016-10-25

This series contains some bug fixes for the mlx5 core and mlx5e driver.

From Daniel:
    - Cache line size determination at runtime, instead of using
      L1_CACHE_BYTES hard coded value, use cache_line_size()
    - Always Query HCA caps after setting them even on reset flow

From Mohamad:
    - Reorder netdev cleanup to uregister netdev before detaching it
      for the kernel to not complain about open resources such as vlans
    - Change the acl enable prototype to return status, for better error
      resiliency
    - Clear health sick bit when starting health poll after reset flow
    - Fix race between PCI error handlers and health work
    - PCI error recovery health care simulation, in case when the kernel
      PCI error handlers are not triggered for some internal firmware errors

From Noa:
    - Avoid passing dma address 0 to firmware when mapping system pages
      to the firmware

From Paul: Some straight forward flow steering fixes
    - Keep autogroups list ordered
    - Fix autogroups groups num not decreasing
    - Correctly initialize last use of flow counters

From Saeed:
    - Choose the nearest LRO timeout to the wanted one
      instead of blindly choosing "dev_cap.lro_timeout[2]"

This series has no conflict with the for-next pull request posted
earlier today ("Mellanox mlx5 core driver updates 2016-10-25").
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents bf911e98 6b276190

drivers/infiniband/hw/mlx5/main.c

+1 −1
Original line number Diff line number Diff line
@@ -1019,7 +1019,7 @@ static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 
	resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);

	if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))

		resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);

	resp.cache_line_size = L1_CACHE_BYTES;

	resp.cache_line_size = cache_line_size();

	resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);

	resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);

	resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);

drivers/infiniband/hw/mlx5/qp.c

+0 −1
Original line number Diff line number Diff line
@@ -52,7 +52,6 @@ enum { 


enum {

	MLX5_IB_SQ_STRIDE	= 6,

	MLX5_IB_CACHE_LINE_SIZE	= 64,

};



static const u32 mlx5_ib_opcode[] = {

drivers/net/ethernet/mellanox/mlx5/core/alloc.c

+26 −5
Original line number Diff line number Diff line
@@ -41,6 +41,13 @@ 


#include "mlx5_core.h"



struct mlx5_db_pgdir {

	struct list_head	list;

	unsigned long	       *bitmap;

	__be32		       *db_page;

	dma_addr_t		db_dma;

};



/* Handling for queue buffers -- we allocate a bunch of memory and

 * register it in a memory region at HCA virtual address 0.

 */
@@ -102,17 +109,28 @@ EXPORT_SYMBOL_GPL(mlx5_buf_free); 
static struct mlx5_db_pgdir *mlx5_alloc_db_pgdir(struct mlx5_core_dev *dev,

						 int node)

{

	u32 db_per_page = PAGE_SIZE / cache_line_size();

	struct mlx5_db_pgdir *pgdir;



	pgdir = kzalloc(sizeof(*pgdir), GFP_KERNEL);

	if (!pgdir)

		return NULL;



	bitmap_fill(pgdir->bitmap, MLX5_DB_PER_PAGE);

	pgdir->bitmap = kcalloc(BITS_TO_LONGS(db_per_page),

				sizeof(unsigned long),

				GFP_KERNEL);



	if (!pgdir->bitmap) {

		kfree(pgdir);

		return NULL;

	}



	bitmap_fill(pgdir->bitmap, db_per_page);



	pgdir->db_page = mlx5_dma_zalloc_coherent_node(dev, PAGE_SIZE,

						       &pgdir->db_dma, node);

	if (!pgdir->db_page) {

		kfree(pgdir->bitmap);

		kfree(pgdir);

		return NULL;

	}
@@ -123,18 +141,19 @@ static struct mlx5_db_pgdir *mlx5_alloc_db_pgdir(struct mlx5_core_dev *dev, 
static int mlx5_alloc_db_from_pgdir(struct mlx5_db_pgdir *pgdir,

				    struct mlx5_db *db)

{

	u32 db_per_page = PAGE_SIZE / cache_line_size();

	int offset;

	int i;



	i = find_first_bit(pgdir->bitmap, MLX5_DB_PER_PAGE);

	if (i >= MLX5_DB_PER_PAGE)

	i = find_first_bit(pgdir->bitmap, db_per_page);

	if (i >= db_per_page)

		return -ENOMEM;



	__clear_bit(i, pgdir->bitmap);



	db->u.pgdir = pgdir;

	db->index   = i;

	offset = db->index * L1_CACHE_BYTES;

	offset = db->index * cache_line_size();

	db->db      = pgdir->db_page + offset / sizeof(*pgdir->db_page);

	db->dma     = pgdir->db_dma  + offset;
@@ -181,14 +200,16 @@ EXPORT_SYMBOL_GPL(mlx5_db_alloc); 


void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db)

{

	u32 db_per_page = PAGE_SIZE / cache_line_size();

	mutex_lock(&dev->priv.pgdir_mutex);



	__set_bit(db->index, db->u.pgdir->bitmap);



	if (bitmap_full(db->u.pgdir->bitmap, MLX5_DB_PER_PAGE)) {

	if (bitmap_full(db->u.pgdir->bitmap, db_per_page)) {

		dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,

				  db->u.pgdir->db_page, db->u.pgdir->db_dma);

		list_del(&db->u.pgdir->list);

		kfree(db->u.pgdir->bitmap);

		kfree(db->u.pgdir);

	}

drivers/net/ethernet/mellanox/mlx5/core/en.h

+5 −0
Original line number Diff line number Diff line
@@ -85,6 +85,9 @@ 
#define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD	(128)



#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ                 (64 * 1024)

#define MLX5E_DEFAULT_LRO_TIMEOUT                       32

#define MLX5E_LRO_TIMEOUT_ARR_SIZE                      4



#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10

#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3

#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
@@ -221,6 +224,7 @@ struct mlx5e_params { 
	struct ieee_ets ets;

#endif

	bool rx_am_enabled;

	u32 lro_timeout;

};



struct mlx5e_tstamp {
@@ -888,5 +892,6 @@ int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev); 
void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);

struct rtnl_link_stats64 *

mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);

u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout);



#endif /* __MLX5_EN_H__ */

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

+17 −4
Original line number Diff line number Diff line
@@ -1971,9 +1971,7 @@ static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv) 
	MLX5_SET(tirc, tirc, lro_max_ip_payload_size,

		 (priv->params.lro_wqe_sz -

		  ROUGH_MAX_L2_L3_HDR_SZ) >> 8);

	MLX5_SET(tirc, tirc, lro_timeout_period_usecs,

		 MLX5_CAP_ETH(priv->mdev,

			      lro_timer_supported_periods[2]));

	MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);

}



void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
@@ -3401,6 +3399,18 @@ static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev, 
	}

}



u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)

{

	int i;



	/* The supported periods are organized in ascending order */

	for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)

		if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)

			break;



	return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);

}



static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,

					struct net_device *netdev,

					const struct mlx5e_profile *profile,
@@ -3419,6 +3429,9 @@ static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev, 
	priv->profile                      = profile;

	priv->ppriv                        = ppriv;



	priv->params.lro_timeout =

		mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);



	priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;



	/* set CQE compression */
@@ -4035,7 +4048,6 @@ void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv) 
	const struct mlx5e_profile *profile = priv->profile;

	struct net_device *netdev = priv->netdev;



	unregister_netdev(netdev);

	destroy_workqueue(priv->wq);

	if (profile->cleanup)

		profile->cleanup(priv);
@@ -4052,6 +4064,7 @@ static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv) 
	for (vport = 1; vport < total_vfs; vport++)

		mlx5_eswitch_unregister_vport_rep(esw, vport);



	unregister_netdev(priv->netdev);

	mlx5e_detach(mdev, vpriv);

	mlx5e_destroy_netdev(mdev, priv);

}