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Commit 588823f9 authored by Arkadi Sharshevsky's avatar Arkadi Sharshevsky Committed by David S. Miller
Browse files

mlxsw: spectrum: Add support for IPv6 MLDv1/2 traps 



Add support for IPv6 MLDv1/2 packet trapping.

Signed-off-by: default avatarArkadi Sharshevsky <arkadis@mellanox.com>
Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 7607dd35

drivers/net/ethernet/mellanox/mlxsw/reg.h

+1 −0
Original line number Diff line number Diff line
@@ -3688,6 +3688,7 @@ enum mlxsw_reg_htgt_trap_group { 
	MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD,

};



/* reg_htgt_trap_group

drivers/net/ethernet/mellanox/mlxsw/spectrum.c

+10 −0
Original line number Diff line number Diff line
@@ -3333,6 +3333,14 @@ static const struct mlxsw_listener mlxsw_sp_listener[] = { 
	MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),

	MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),

	MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),

	MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,

			  false),

	MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,

			     false),

	MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,

			     false),

	MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,

			     false),

	/* L3 traps */

	MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),

	MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
@@ -3377,6 +3385,7 @@ static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core) 
			burst_size = 7;

			break;

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:

			rate = 16 * 1024;

			burst_size = 10;

			break;
@@ -3441,6 +3450,7 @@ static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core) 
			break;

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:

			priority = 3;

			tc = 3;

			break;

drivers/net/ethernet/mellanox/mlxsw/trap.h

+4 −0
Original line number Diff line number Diff line
@@ -63,6 +63,10 @@ enum { 
	MLXSW_TRAP_ID_LBERROR = 0x54,

	MLXSW_TRAP_ID_OSPF = 0x55,

	MLXSW_TRAP_ID_IP2ME = 0x5F,

	MLXSW_TRAP_ID_IPV6_MLDV12_LISTENER_QUERY = 0x65,

	MLXSW_TRAP_ID_IPV6_MLDV1_LISTENER_REPORT = 0x66,

	MLXSW_TRAP_ID_IPV6_MLDV1_LISTENER_DONE = 0x67,

	MLXSW_TRAP_ID_IPV6_MLDV2_LISTENER_REPORT = 0x68,

	MLXSW_TRAP_ID_RTR_INGRESS0 = 0x70,

	MLXSW_TRAP_ID_BGP_IPV4 = 0x88,

	MLXSW_TRAP_ID_HOST_MISS_IPV4 = 0x90,