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Commit 581df9e1 authored by Nicolas Ferre's avatar Nicolas Ferre Committed by David S. Miller
Browse files

net/macb: fix ISR clear-on-write behavior only for some SoC 



Commit 749a2b66 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using the Design Configuration Register 1 information and a capability
property to actually activate this clear-on-write behavior on ISR.

Reported-by: default avatarHein Tibosch <hein_tibosch@yahoo.es>
Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: default avatarHein Tibosch <hein_tibosch@yahoo.es>
Acked-by: default avatarJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent faff57a9

drivers/net/ethernet/cadence/macb.c

+16 −2
Original line number Diff line number Diff line
@@ -485,6 +485,7 @@ static void macb_tx_interrupt(struct macb *bp) 
	status = macb_readl(bp, TSR);

	macb_writel(bp, TSR, status);



	if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)

		macb_writel(bp, ISR, MACB_BIT(TCOMP));



	netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
@@ -738,6 +739,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id) 
			 * now.

			 */

			macb_writel(bp, IDR, MACB_RX_INT_FLAGS);

			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)

				macb_writel(bp, ISR, MACB_BIT(RCOMP));



			if (napi_schedule_prep(&bp->napi)) {
@@ -1062,6 +1064,17 @@ static void macb_configure_dma(struct macb *bp) 
	}

}



/*

 * Configure peripheral capacities according to integration options used

 */

static void macb_configure_caps(struct macb *bp)

{

	if (macb_is_gem(bp)) {

		if (GEM_BF(IRQCOR, gem_readl(bp, DCFG1)) == 0)

			bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;

	}

}



static void macb_init_hw(struct macb *bp)

{

	u32 config;
@@ -1084,6 +1097,7 @@ static void macb_init_hw(struct macb *bp) 
	bp->duplex = DUPLEX_HALF;



	macb_configure_dma(bp);

	macb_configure_caps(bp);



	/* Initialize TX and RX buffers */

	macb_writel(bp, RBQP, bp->rx_ring_dma);

drivers/net/ethernet/cadence/macb.h

+7 −0
Original line number Diff line number Diff line
@@ -300,6 +300,8 @@ 
#define MACB_REV_SIZE				16



/* Bitfields in DCFG1. */

#define GEM_IRQCOR_OFFSET			23

#define GEM_IRQCOR_SIZE				1

#define GEM_DBWDEF_OFFSET			25

#define GEM_DBWDEF_SIZE				3
@@ -323,6 +325,9 @@ 
#define MACB_MAN_READ				2

#define MACB_MAN_CODE				2



/* Capability mask bits */

#define MACB_CAPS_ISR_CLEAR_ON_WRITE		0x1



/* Bit manipulation macros */

#define MACB_BIT(name)					\

	(1 << MACB_##name##_OFFSET)
@@ -574,6 +579,8 @@ struct macb { 
	unsigned int 		speed;

	unsigned int 		duplex;



	u32			caps;



	phy_interface_t		phy_interface;



	/* AT91RM9200 transmit */