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Commit 57a8f32e authored by Sonic Zhang's avatar Sonic Zhang Committed by Ben Dooks
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i2c: Blackfin TWI: fix REPEAT START mode doesn't repeat 



Avoid rewrite TWI MASTER_CTL reg when issue next message
In i2c repeat transfer mode, byte count of next message should be filled
into part of the TWI MASTER_CTL reg when interrupt MCOMP of last
message transfer is triggered. But, other bits in this reg should
not be touched.

Signed-off-by: default avatarSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
[ben-linux@fluff.org: shorted subject]
Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
parent 9528d1c7

drivers/i2c/busses/i2c-bfin-twi.c

+7 −8
Original line number Diff line number Diff line
@@ -196,8 +196,6 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface) 
			/* remove restart bit and enable master receive */

			write_MASTER_CTL(iface,

				read_MASTER_CTL(iface) & ~RSTART);

			write_MASTER_CTL(iface,

				read_MASTER_CTL(iface) | MEN | MDIR);

			SSYNC();

		} else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&

				iface->cur_msg+1 < iface->msg_num) {
@@ -223,17 +221,18 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface) 


			if (iface->pmsg[iface->cur_msg].len <= 255)

					write_MASTER_CTL(iface,

				iface->pmsg[iface->cur_msg].len << 6);

					(read_MASTER_CTL(iface) &

					(~(0xff << 6))) |

				(iface->pmsg[iface->cur_msg].len << 6));

			else {

				write_MASTER_CTL(iface, 0xff << 6);

				write_MASTER_CTL(iface,

					(read_MASTER_CTL(iface) |

					(0xff << 6)));

				iface->manual_stop = 1;

			}

			/* remove restart bit and enable master receive */

			write_MASTER_CTL(iface,

				read_MASTER_CTL(iface) & ~RSTART);

			write_MASTER_CTL(iface, read_MASTER_CTL(iface) |

				MEN | ((iface->read_write == I2C_SMBUS_READ) ?

				MDIR : 0));

			SSYNC();

		} else {

			iface->result = 1;