Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 573a652f authored by Lennert Buytenhek's avatar Lennert Buytenhek Committed by Nicolas Pitre
Browse files

ARM: Add Tauros2 L2 cache controller support 



Support for the Tauros2 L2 cache controller as used with the PJ1
and PJ4 CPUs.

Signed-off-by: default avatarLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: default avatarSaeed Bishara <saeed@marvell.com>
Signed-off-by: default avatarNicolas Pitre <nico@marvell.com>
parent edabd38e

arch/arm/configs/dove_defconfig

+3 −1
Original line number Diff line number Diff line 
#

# Automatically generated make config: don't edit

# Linux kernel version: 2.6.32-rc6

# Tue Nov 24 13:48:39 2009

# Tue Nov 24 13:51:23 2009

#

CONFIG_ARM=y

CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -207,6 +207,8 @@ CONFIG_ARM_THUMB=y 
# CONFIG_CPU_ICACHE_DISABLE is not set

# CONFIG_CPU_DCACHE_DISABLE is not set

# CONFIG_CPU_BPREDICT_DISABLE is not set

CONFIG_OUTER_CACHE=y

CONFIG_CACHE_TAUROS2=y

CONFIG_ARM_L1_CACHE_SHIFT=5

# CONFIG_ARM_ERRATA_411920 is not set

arch/arm/include/asm/hardware/cache-tauros2.h

0 → 100644
+11 −0
Original line number Diff line number Diff line 
/*

 * arch/arm/include/asm/hardware/cache-tauros2.h

 *

 * Copyright (C) 2008 Marvell Semiconductor

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2. This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */



extern void __init tauros2_init(void);

arch/arm/mach-dove/common.c

+4 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
#include <asm/page.h>

#include <asm/setup.h>

#include <asm/timex.h>

#include <asm/hardware/cache-tauros2.h>

#include <asm/mach/map.h>

#include <asm/mach/time.h>

#include <asm/mach/pci.h>
@@ -760,6 +761,9 @@ void __init dove_init(void) 
	printk(KERN_INFO "Dove 88AP510 SoC, ");

	printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000);



#ifdef CONFIG_CACHE_TAUROS2

	tauros2_init();

#endif

	dove_setup_cpu_mbus();



	dove_ge00_shared_data.t_clk = tclk;

arch/arm/mm/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -764,6 +764,15 @@ config CACHE_L2X0 
	help

	  This option enables the L2x0 PrimeCell.



config CACHE_TAUROS2

	bool "Enable the Tauros2 L2 cache controller"

	depends on ARCH_DOVE

	default y

	select OUTER_CACHE

	help

	  This option enables the Tauros2 L2 cache controller (as

	  found on PJ1/PJ4).



config CACHE_XSC3L2

	bool "Enable the L2 cache on XScale3"

	depends on CPU_XSC3

arch/arm/mm/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -87,4 +87,4 @@ obj-$(CONFIG_CPU_V7) += proc-v7.o 
obj-$(CONFIG_CACHE_FEROCEON_L2)	+= cache-feroceon-l2.o

obj-$(CONFIG_CACHE_L2X0)	+= cache-l2x0.o

obj-$(CONFIG_CACHE_XSC3L2)	+= cache-xsc3l2.o

obj-$(CONFIG_CACHE_TAUROS2)	+= cache-tauros2.o