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Commit 572d46df authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "drivers: llcc: Support targets that can write to llcc registers"

parents bc153da3 9942b28e

Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt

+7 −0
Original line number Diff line number Diff line
@@ -31,6 +31,13 @@ Properties: 
		    It's used for llcc cache single and double bit error detection

		    and reporting.



- cap-based-alloc-and-pwr-collapse:

	Usage: optional

	Value Type: Boolean

	Definition: Property to express that HLOS can enable/disable capacity

	based allocation and power collapse retention for a client. Include

	this property to set it. If not set, it will be treated as false.



Example:



	cache-controller@9200000 {

drivers/soc/qcom/llcc-slice.c

+23 −0
Original line number Diff line number Diff line
@@ -45,6 +45,9 @@ 
#define LLCC_TRP_WRSC_EN              0x21F20

#define LLCC_WRSC_SCID_EN(n)          BIT(n)



#define LLCC_TRP_PCB_ACT	      0x21F04

#define LLCC_TRP_SCID_DIS_CAP_ALLOC   0x21F00



#define BANK_OFFSET_STRIDE            0x80000



static struct llcc_drv_data *drv_data;
@@ -227,9 +230,13 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev) 
	u32 attr0_val;

	u32 max_cap_cacheline;

	u32 sz;

	u32 pcb = 0;

	u32 cad = 0;

	int ret = 0;

	const struct llcc_slice_config *llcc_table;

	struct llcc_slice_desc desc;

	bool cap_based_alloc_and_pwr_collapse =

		drv_data->cap_based_alloc_and_pwr_collapse;



	sz = drv_data->cfg_size;

	llcc_table = drv_data->cfg;
@@ -278,6 +285,18 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev) 
				return ret;

		}



		if (cap_based_alloc_and_pwr_collapse) {

			cad |= llcc_table[i].dis_cap_alloc <<

				llcc_table[i].slice_id;

			regmap_write(drv_data->bcast_regmap,

					LLCC_TRP_SCID_DIS_CAP_ALLOC, cad);



			pcb |= llcc_table[i].retain_on_pc <<

					llcc_table[i].slice_id;

			regmap_write(drv_data->bcast_regmap,

					LLCC_TRP_PCB_ACT, pcb);

		}



		if (llcc_table[i].activate_on_init) {

			desc.slice_id = llcc_table[i].slice_id;

			ret = llcc_slice_activate(&desc);
@@ -342,6 +361,10 @@ int qcom_llcc_probe(struct platform_device *pdev, 
	if (!drv_data->offsets)

		return -ENOMEM;



	drv_data->cap_based_alloc_and_pwr_collapse =

		of_property_read_bool(pdev->dev.of_node,

				      "cap-based-alloc-and-pwr-collapse");



	for (i = 0; i < num_banks; i++)

		drv_data->offsets[i] = i * BANK_OFFSET_STRIDE;

include/linux/soc/qcom/llcc-qcom.h

+1 −0
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ struct llcc_drv_data { 
	unsigned long *bitmap;

	u32 *offsets;

	int ecc_irq;

	bool cap_based_alloc_and_pwr_collapse;

};



/**