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Commit 5692fcc6 authored by Guilherme G. Piccoli's avatar Guilherme G. Piccoli Committed by Paul E. McKenney
Browse files

doc: Rewrite confusing statement about memory barriers 



The "Write (or store) memory barriers" bullet of the "Variety of memory
barriers" section, calls out a sequential order of stores, which is
confusing since sequential ordering is not guaranteed.

This commit therefore rewords to avoid mentioning a sequence of stores
to clarify the intent.

Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Signed-off-by: default avatarGuilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com>
Signed-off-by: default avatarPaul E. McKenney <paulmck@linux.vnet.ibm.com>
parent d92f842b

Documentation/memory-barriers.txt

+2 −2
Original line number Diff line number Diff line
@@ -383,8 +383,8 @@ Memory barriers come in four basic varieties: 
     to have any effect on loads.



     A CPU can be viewed as committing a sequence of store operations to the

     memory system as time progresses.  All stores before a write barrier will

     occur in the sequence _before_ all the stores after the write barrier.

     memory system as time progresses.  All stores _before_ a write barrier

     will occur _before_ all the stores after the write barrier.



     [!] Note that write barriers should normally be paired with read or data

     dependency barriers; see the "SMP barrier pairing" subsection.