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Commit 567be786 authored by jpinto's avatar jpinto Committed by David S. Miller
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stmmac: CSR clock configuration fix 



When testing stmmac with my QoS reference design I checked a problem in the
CSR clock configuration that was impossibilitating the phy discovery, since
every read operation returned 0x0000ffff. This patch fixes the issue.

Signed-off-by: default avatarJoao Pinto <jpinto@synopsys.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 2e3d5fa4

drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

+1 −1
Original line number Diff line number Diff line
@@ -539,7 +539,7 @@ struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins, 
	mac->mii.reg_shift = 6;

	mac->mii.reg_mask = 0x000007C0;

	mac->mii.clk_csr_shift = 2;

	mac->mii.clk_csr_mask = 0xF;

	mac->mii.clk_csr_mask = GENMASK(5, 2);



	/* Get and dump the chip ID */

	*synopsys_id = stmmac_get_synopsys_id(hwid);

drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c

+1 −1
Original line number Diff line number Diff line
@@ -197,7 +197,7 @@ struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id) 
	mac->mii.reg_shift = 6;

	mac->mii.reg_mask = 0x000007C0;

	mac->mii.clk_csr_shift = 2;

	mac->mii.clk_csr_mask = 0xF;

	mac->mii.clk_csr_mask = GENMASK(5, 2);



	/* Synopsys Id is not available on old chips */

	*synopsys_id = 0;

drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c

+4 −4
Original line number Diff line number Diff line
@@ -81,8 +81,8 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) 
	value |= (phyaddr << priv->hw->mii.addr_shift)

		& priv->hw->mii.addr_mask;

	value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;

	value |= (priv->clk_csr & priv->hw->mii.clk_csr_mask)

		<< priv->hw->mii.clk_csr_shift;

	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)

		& priv->hw->mii.clk_csr_mask;

	if (priv->plat->has_gmac4)

		value |= MII_GMAC4_READ;
@@ -122,8 +122,8 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, 
		& priv->hw->mii.addr_mask;

	value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;



	value |= ((priv->clk_csr & priv->hw->mii.clk_csr_mask)

		<< priv->hw->mii.clk_csr_shift);

	value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)

		& priv->hw->mii.clk_csr_mask;

	if (priv->plat->has_gmac4)

		value |= MII_GMAC4_WRITE;