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Commit 565602d7 authored by Maarten Lankhorst's avatar Maarten Lankhorst
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drm/i915: Do not acquire crtc state to check clock during modeset, v4. 



Parallel modesets are still not allowed, but this will allow updating
a different crtc during a modeset if the clock is not changed.

Additionally when all pipes are DPMS off the cdclk will be lowered
to the minimum allowed.

Changes since v1:
- Add dev_priv->active_crtcs for tracking which crtcs are active.
- Rename min_cdclk to min_pixclk and move to dev_priv.
- Add a active_crtcs mask which is updated atomically.
- Add intel_atomic_state->modeset which is set on modesets.
- Commit new pixclk/active_crtcs right after state swap.
Changes since v2:
- Make the changes related to max_pixel_rate calculations more readable.
Changes since v3:
- Add cherryview and missing WARN_ON to readout.

Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
parent bf8a0af0

drivers/gpu/drm/i915/i915_drv.h

+5 −0
Original line number Original line Diff line number Diff line
@@ -1819,8 +1819,13 @@ struct drm_i915_private { 
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];

	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];

#endif

#endif





	/* dpll and cdclk state is protected by connection_mutex */

	int num_shared_dpll;

	int num_shared_dpll;

	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];

	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];



	unsigned int active_crtcs;

	unsigned int min_pixclk[I915_MAX_PIPES];



	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];

	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];





	struct i915_workarounds workarounds;

	struct i915_workarounds workarounds;

drivers/gpu/drm/i915/intel_atomic.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -308,5 +308,5 @@ void intel_atomic_state_clear(struct drm_atomic_state *s) 
{

{

	struct intel_atomic_state *state = to_intel_atomic_state(s);

	struct intel_atomic_state *state = to_intel_atomic_state(s);

	drm_atomic_state_default_clear(&state->base);

	drm_atomic_state_default_clear(&state->base);

	state->dpll_set = false;

	state->dpll_set = state->modeset = false;

}
 
}

drivers/gpu/drm/i915/intel_display.c

+104 −39
Original line number Original line Diff line number Diff line
@@ -6063,22 +6063,31 @@ static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, 
static int intel_mode_max_pixclk(struct drm_device *dev,

static int intel_mode_max_pixclk(struct drm_device *dev,

				 struct drm_atomic_state *state)

				 struct drm_atomic_state *state)

{

{

	struct intel_crtc *intel_crtc;

	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);

	struct intel_crtc_state *crtc_state;

	struct drm_i915_private *dev_priv = dev->dev_private;

	int max_pixclk = 0;

	struct drm_crtc *crtc;

	struct drm_crtc_state *crtc_state;

	unsigned max_pixclk = 0, i;

	enum pipe pipe;





	for_each_intel_crtc(dev, intel_crtc) {

	memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,

		crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);

	       sizeof(intel_state->min_pixclk));

		if (IS_ERR(crtc_state))

			return PTR_ERR(crtc_state);





		if (!crtc_state->base.enable)

	for_each_crtc_in_state(state, crtc, crtc_state, i) {

			continue;

		int pixclk = 0;





		max_pixclk = max(max_pixclk,

		if (crtc_state->enable)

				 crtc_state->base.adjusted_mode.crtc_clock);

			pixclk = crtc_state->adjusted_mode.crtc_clock;



		intel_state->min_pixclk[i] = pixclk;

	}

	}





	if (!intel_state->active_crtcs)

		return 0;



	for_each_pipe(dev_priv, pipe)

		max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);



	return max_pixclk;

	return max_pixclk;

}

}
@@ -6383,6 +6392,9 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) 
	for_each_power_domain(domain, domains)

	for_each_power_domain(domain, domains)

		intel_display_power_put(dev_priv, domain);

		intel_display_power_put(dev_priv, domain);

	intel_crtc->enabled_power_domains = 0;

	intel_crtc->enabled_power_domains = 0;



	dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);

	dev_priv->min_pixclk[intel_crtc->pipe] = 0;

}

}





/*

/*
@@ -9679,29 +9691,41 @@ static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) 
/* compute the max rate for new configuration */

/* compute the max rate for new configuration */

static int ilk_max_pixel_rate(struct drm_atomic_state *state)

static int ilk_max_pixel_rate(struct drm_atomic_state *state)

{

{

	struct intel_crtc *intel_crtc;

	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);

	struct drm_i915_private *dev_priv = state->dev->dev_private;

	struct drm_crtc *crtc;

	struct drm_crtc_state *cstate;

	struct intel_crtc_state *crtc_state;

	struct intel_crtc_state *crtc_state;

	int max_pixel_rate = 0;

	unsigned max_pixel_rate = 0, i;

	enum pipe pipe;





	for_each_intel_crtc(state->dev, intel_crtc) {

	memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,

		int pixel_rate;

	       sizeof(intel_state->min_pixclk));





		crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);

	for_each_crtc_in_state(state, crtc, cstate, i) {

		if (IS_ERR(crtc_state))

		int pixel_rate;

			return PTR_ERR(crtc_state);





		if (!crtc_state->base.enable)

		crtc_state = to_intel_crtc_state(cstate);

		if (!crtc_state->base.enable) {

			intel_state->min_pixclk[i] = 0;

			continue;

			continue;

		}





		pixel_rate = ilk_pipe_pixel_rate(crtc_state);

		pixel_rate = ilk_pipe_pixel_rate(crtc_state);





		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */

		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */

		if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)

		if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)

			pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);

			pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);





		max_pixel_rate = max(max_pixel_rate, pixel_rate);

		intel_state->min_pixclk[i] = pixel_rate;

	}

	}





	if (!intel_state->active_crtcs)

		return 0;



	for_each_pipe(dev_priv, pipe)

		max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);



	return max_pixel_rate;

	return max_pixel_rate;

}

}
@@ -13208,15 +13232,27 @@ static int intel_modeset_all_pipes(struct drm_atomic_state *state) 




static int intel_modeset_checks(struct drm_atomic_state *state)

static int intel_modeset_checks(struct drm_atomic_state *state)

{

{

	struct drm_device *dev = state->dev;

	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = state->dev->dev_private;

	int ret;

	struct drm_crtc *crtc;

	struct drm_crtc_state *crtc_state;

	int ret = 0, i;





	if (!check_digital_port_conflicts(state)) {

	if (!check_digital_port_conflicts(state)) {

		DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");

		DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");

		return -EINVAL;

		return -EINVAL;

	}

	}





	intel_state->modeset = true;

	intel_state->active_crtcs = dev_priv->active_crtcs;



	for_each_crtc_in_state(state, crtc, crtc_state, i) {

		if (crtc_state->active)

			intel_state->active_crtcs |= 1 << i;

		else

			intel_state->active_crtcs &= ~(1 << i);

	}



	/*

	/*

	 * See if the config requires any additional preparation, e.g.

	 * See if the config requires any additional preparation, e.g.

	 * to adjust global state with pipes off.  We need to do this

	 * to adjust global state with pipes off.  We need to do this
@@ -13240,7 +13276,7 @@ static int intel_modeset_checks(struct drm_atomic_state *state) 




	intel_modeset_clear_plls(state);

	intel_modeset_clear_plls(state);





	if (IS_HASWELL(dev))

	if (IS_HASWELL(dev_priv))

		return haswell_mode_set_planes_workaround(state);

		return haswell_mode_set_planes_workaround(state);





	return 0;

	return 0;
@@ -13458,12 +13494,12 @@ static int intel_atomic_commit(struct drm_device *dev, 
			       struct drm_atomic_state *state,

			       struct drm_atomic_state *state,

			       bool async)

			       bool async)

{

{

	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_crtc_state *crtc_state;

	struct drm_crtc_state *crtc_state;

	struct drm_crtc *crtc;

	struct drm_crtc *crtc;

	int ret = 0;

	int ret = 0, i;

	int i;

	bool hw_check = intel_state->modeset;

	bool any_ms = false;





	ret = intel_atomic_prepare_commit(dev, state, async);

	ret = intel_atomic_prepare_commit(dev, state, async);

	if (ret) {

	if (ret) {
@@ -13474,13 +13510,18 @@ static int intel_atomic_commit(struct drm_device *dev, 
	drm_atomic_helper_swap_state(dev, state);

	drm_atomic_helper_swap_state(dev, state);

	dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;

	dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;





	if (intel_state->modeset) {

		memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,

		       sizeof(intel_state->min_pixclk));

		dev_priv->active_crtcs = intel_state->active_crtcs;

	}



	for_each_crtc_in_state(state, crtc, crtc_state, i) {

	for_each_crtc_in_state(state, crtc, crtc_state, i) {

		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);





		if (!needs_modeset(crtc->state))

		if (!needs_modeset(crtc->state))

			continue;

			continue;





		any_ms = true;

		intel_pre_plane_update(intel_crtc);

		intel_pre_plane_update(intel_crtc);





		if (crtc_state->active) {

		if (crtc_state->active) {
@@ -13505,7 +13546,7 @@ static int intel_atomic_commit(struct drm_device *dev, 
	 * update the the output configuration. */

	 * update the the output configuration. */

	intel_modeset_update_crtc_state(state);

	intel_modeset_update_crtc_state(state);





	if (any_ms) {

	if (intel_state->modeset) {

		intel_shared_dpll_commit(state);

		intel_shared_dpll_commit(state);





		drm_atomic_helper_update_legacy_modeset_state(state->dev, state);

		drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
@@ -13532,7 +13573,7 @@ static int intel_atomic_commit(struct drm_device *dev, 
			put_domains = modeset_get_crtc_power_domains(crtc);

			put_domains = modeset_get_crtc_power_domains(crtc);





			/* make sure intel_modeset_check_state runs */

			/* make sure intel_modeset_check_state runs */

			any_ms = true;

			hw_check = true;

		}

		}





		if (!modeset)

		if (!modeset)
@@ -13559,7 +13600,7 @@ static int intel_atomic_commit(struct drm_device *dev, 
	drm_atomic_helper_cleanup_planes(dev, state);

	drm_atomic_helper_cleanup_planes(dev, state);

	mutex_unlock(&dev->struct_mutex);

	mutex_unlock(&dev->struct_mutex);





	if (any_ms)

	if (hw_check)

		intel_modeset_check_state(dev, state);

		intel_modeset_check_state(dev, state);





	drm_atomic_state_free(state);

	drm_atomic_state_free(state);
@@ -15591,16 +15632,40 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) 
	struct intel_connector *connector;

	struct intel_connector *connector;

	int i;

	int i;





	dev_priv->active_crtcs = 0;



	for_each_intel_crtc(dev, crtc) {

	for_each_intel_crtc(dev, crtc) {

		__drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);

		struct intel_crtc_state *crtc_state = crtc->config;

		memset(crtc->config, 0, sizeof(*crtc->config));

		int pixclk = 0;

		crtc->config->base.crtc = &crtc->base;





		crtc->active = dev_priv->display.get_pipe_config(crtc,

		__drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);

								 crtc->config);

		memset(crtc_state, 0, sizeof(*crtc_state));

		crtc_state->base.crtc = &crtc->base;





		crtc->base.state->active = crtc->active;

		crtc_state->base.active = crtc_state->base.enable =

		crtc->base.enabled = crtc->active;

			dev_priv->display.get_pipe_config(crtc, crtc_state);



		crtc->base.enabled = crtc_state->base.enable;

		crtc->active = crtc_state->base.active;



		if (crtc_state->base.active) {

			dev_priv->active_crtcs |= 1 << crtc->pipe;



			if (IS_BROADWELL(dev_priv)) {

				pixclk = ilk_pipe_pixel_rate(crtc_state);



				/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */

				if (crtc_state->ips_enabled)

					pixclk = DIV_ROUND_UP(pixclk * 100, 95);

			} else if (IS_VALLEYVIEW(dev_priv) ||

				   IS_CHERRYVIEW(dev_priv) ||

				   IS_BROXTON(dev_priv))

				pixclk = crtc_state->base.adjusted_mode.crtc_clock;

			else

				WARN_ON(dev_priv->display.modeset_calc_cdclk);

		}



		dev_priv->min_pixclk[crtc->pipe] = pixclk;





		readout_plane_state(crtc);

		readout_plane_state(crtc);

drivers/gpu/drm/i915/intel_drv.h

+6 −1
Original line number Original line Diff line number Diff line
@@ -246,7 +246,12 @@ struct intel_atomic_state { 
	struct drm_atomic_state base;

	struct drm_atomic_state base;





	unsigned int cdclk;

	unsigned int cdclk;

	bool dpll_set;



	bool dpll_set, modeset;



	unsigned int active_crtcs;

	unsigned int min_pixclk[I915_MAX_PIPES];



	struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];

	struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];

	struct intel_wm_config wm_config;

	struct intel_wm_config wm_config;

};

};