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Commit 563ce4d5 authored by Philip Avinash's avatar Philip Avinash Committed by Paul Walmsley
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ARM: AM33XX: clk: Add clock node for EHRPWM TBCLK 



EHRPWM module requires explicit clock gating of TBCLK from control
module. Hence add TBCLK clock node in clock tree for EHRPWM modules.

Signed-off-by: default avatarPhilip Avinash <avinashphilip@ti.com>
[bigeasy: remove CK_AM33XX]
Signed-off-by: default avatarSebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent 1919f0f7

arch/arm/mach-omap2/cclock33xx_data.c

+30 −0
Original line number Diff line number Diff line
@@ -862,6 +862,33 @@ static struct clk_hw_omap wdt1_fck_hw = { 


DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);



static const char *pwmss_clk_parents[] = {

	"dpll_per_m2_ck",

};



static const struct clk_ops ehrpwm_tbclk_ops = {

	.enable		= &omap2_dflt_clk_enable,

	.disable	= &omap2_dflt_clk_disable,

};



DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",

			 NULL, NULL, 0,

			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),

			 AM33XX_PWMSS0_TBCLKEN_SHIFT,

			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);



DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",

			 NULL, NULL, 0,

			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),

			 AM33XX_PWMSS1_TBCLKEN_SHIFT,

			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);



DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",

			 NULL, NULL, 0,

			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),

			 AM33XX_PWMSS2_TBCLKEN_SHIFT,

			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);



/*

 * clkdev

 */
@@ -942,6 +969,9 @@ static struct omap_clk am33xx_clks[] = { 
	CLK(NULL,	"clkout2_div_ck",	&clkout2_div_ck),

	CLK(NULL,	"timer_32k_ck",		&clkdiv32k_ick),

	CLK(NULL,	"timer_sys_ck",		&sys_clkin_ck),

	CLK("48300200.ehrpwm",	"tbclk",	&ehrpwm0_tbclk),

	CLK("48302200.ehrpwm",	"tbclk",	&ehrpwm1_tbclk),

	CLK("48304200.ehrpwm",	"tbclk",	&ehrpwm2_tbclk),

};

arch/arm/mach-omap2/control.h

+8 −0
Original line number Diff line number Diff line
@@ -358,6 +358,14 @@ 
#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH		0x2

#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK		(0x3 << 22)



/* AM33XX PWMSS Control register */

#define AM33XX_PWMSS_TBCLK_CLKCTRL			0x664



/* AM33XX  PWMSS Control bitfields */

#define AM33XX_PWMSS0_TBCLKEN_SHIFT			0

#define AM33XX_PWMSS1_TBCLKEN_SHIFT			1

#define AM33XX_PWMSS2_TBCLKEN_SHIFT			2



/* CONTROL OMAP STATUS register to identify OMAP3 features */

#define OMAP3_CONTROL_OMAP_STATUS	0x044c