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Commit 54f4bbd8 authored by Stefan Agner's avatar Stefan Agner Committed by Greg Kroah-Hartman
Browse files

ARM: 8843/1: use unified assembler in headers 



[ Upstream commit c001899a5d6c2d7a0f3b75b2307ddef137fb46a6 ]

Use unified assembler syntax (UAL) in headers. Divided syntax is
considered deprecated. This will also allow to build the kernel
using LLVM's integrated assembler.

Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
Acked-by: default avatarNicolas Pitre <nico@linaro.org>
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 6dea0088

arch/arm/include/asm/assembler.h

+6 −6
Original line number Diff line number Diff line
@@ -374,9 +374,9 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) 
	.macro	usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()

9999:

	.if	\inc == 1

	\instr\cond\()b\()\t\().w \reg, [\ptr, #\off]

	\instr\()b\t\cond\().w \reg, [\ptr, #\off]

	.elseif	\inc == 4

	\instr\cond\()\t\().w \reg, [\ptr, #\off]

	\instr\t\cond\().w \reg, [\ptr, #\off]

	.else

	.error	"Unsupported inc macro argument"

	.endif
@@ -415,9 +415,9 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) 
	.rept	\rept

9999:

	.if	\inc == 1

	\instr\cond\()b\()\t \reg, [\ptr], #\inc

	\instr\()b\t\cond \reg, [\ptr], #\inc

	.elseif	\inc == 4

	\instr\cond\()\t \reg, [\ptr], #\inc

	\instr\t\cond \reg, [\ptr], #\inc

	.else

	.error	"Unsupported inc macro argument"

	.endif
@@ -458,7 +458,7 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) 
	.macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req

#ifndef CONFIG_CPU_USE_DOMAINS

	adds	\tmp, \addr, #\size - 1

	sbcccs	\tmp, \tmp, \limit

	sbcscc	\tmp, \tmp, \limit

	bcs	\bad

#ifdef CONFIG_CPU_SPECTRE

	movcs	\addr, #0
@@ -472,7 +472,7 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) 
	sub	\tmp, \limit, #1

	subs	\tmp, \tmp, \addr	@ tmp = limit - 1 - addr

	addhs	\tmp, \tmp, #1		@ if (tmp >= 0) {

	subhss	\tmp, \tmp, \size	@ tmp = limit - (addr + size) }

	subshs	\tmp, \tmp, \size	@ tmp = limit - (addr + size) }

	movlo	\addr, #0		@ if (tmp < 0) addr = NULL

	csdb

#endif

arch/arm/include/asm/vfpmacros.h

+4 −4
Original line number Diff line number Diff line
@@ -29,13 +29,13 @@ 
	ldr	\tmp, =elf_hwcap		    @ may not have MVFR regs

	ldr	\tmp, [\tmp, #0]

	tst	\tmp, #HWCAP_VFPD32

	ldcnel	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d16-d31}

	ldclne	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d16-d31}

	addeq	\base, \base, #32*4		    @ step over unused register space

#else

	VFPFMRX	\tmp, MVFR0			    @ Media and VFP Feature Register 0

	and	\tmp, \tmp, #MVFR0_A_SIMD_MASK	    @ A_SIMD field

	cmp	\tmp, #2			    @ 32 x 64bit registers?

	ldceql	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d16-d31}

	ldcleq	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d16-d31}

	addne	\base, \base, #32*4		    @ step over unused register space

#endif

#endif
@@ -53,13 +53,13 @@ 
	ldr	\tmp, =elf_hwcap		    @ may not have MVFR regs

	ldr	\tmp, [\tmp, #0]

	tst	\tmp, #HWCAP_VFPD32

	stcnel	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d16-d31}

	stclne	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d16-d31}

	addeq	\base, \base, #32*4		    @ step over unused register space

#else

	VFPFMRX	\tmp, MVFR0			    @ Media and VFP Feature Register 0

	and	\tmp, \tmp, #MVFR0_A_SIMD_MASK	    @ A_SIMD field

	cmp	\tmp, #2			    @ 32 x 64bit registers?

	stceql	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d16-d31}

	stcleq	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d16-d31}

	addne	\base, \base, #32*4		    @ step over unused register space

#endif

#endif

arch/arm/lib/bitops.h

+4 −4
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ 
ENTRY(	\name		)

UNWIND(	.fnstart	)

	ands	ip, r1, #3

	strneb	r1, [ip]		@ assert word-aligned

	strbne	r1, [ip]		@ assert word-aligned

	mov	r2, #1

	and	r3, r0, #31		@ Get bit offset

	mov	r0, r0, lsr #5
@@ -32,7 +32,7 @@ ENDPROC(\name ) 
ENTRY(	\name		)

UNWIND(	.fnstart	)

	ands	ip, r1, #3

	strneb	r1, [ip]		@ assert word-aligned

	strbne	r1, [ip]		@ assert word-aligned

	mov	r2, #1

	and	r3, r0, #31		@ Get bit offset

	mov	r0, r0, lsr #5
@@ -62,7 +62,7 @@ ENDPROC(\name ) 
ENTRY(	\name		)

UNWIND(	.fnstart	)

	ands	ip, r1, #3

	strneb	r1, [ip]		@ assert word-aligned

	strbne	r1, [ip]		@ assert word-aligned

	and	r2, r0, #31

	mov	r0, r0, lsr #5

	mov	r3, #1
@@ -89,7 +89,7 @@ ENDPROC(\name ) 
ENTRY(	\name		)

UNWIND(	.fnstart	)

	ands	ip, r1, #3

	strneb	r1, [ip]		@ assert word-aligned

	strbne	r1, [ip]		@ assert word-aligned

	and	r3, r0, #31

	mov	r0, r0, lsr #5

	save_and_disable_irqs ip