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Commit 549300ce authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/vi: move uvd tiling config setup into uvd code 



Split uvd and gfx programming.

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c458fe94

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+0 −12
Original line number Diff line number Diff line
@@ -43,9 +43,6 @@ 
#include "gca/gfx_8_0_sh_mask.h"

#include "gca/gfx_8_0_enum.h"



#include "uvd/uvd_5_0_d.h"

#include "uvd/uvd_5_0_sh_mask.h"



#include "dce/dce_10_0_d.h"

#include "dce/dce_10_0_sh_mask.h"
@@ -2695,9 +2692,6 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) 
	WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

	WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

	WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);

	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);



	gfx_v8_0_tiling_mode_table_init(adev);
@@ -3955,12 +3949,6 @@ static void gfx_v8_0_print_status(void *handle) 
		 RREG32(mmHDP_ADDR_CONFIG));

	dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",

		 RREG32(mmDMIF_ADDR_CALC));

	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",

		 RREG32(mmUVD_UDEC_ADDR_CONFIG));

	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",

		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));

	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",

		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));



	dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",

		 RREG32(mmCP_MEQ_THRESHOLDS));

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

+10 −0
Original line number Diff line number Diff line
@@ -279,6 +279,10 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) 
	size = AMDGPU_UVD_HEAP_SIZE;

	WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);

	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);



	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

}



/**
@@ -724,6 +728,12 @@ static void uvd_v5_0_print_status(void *handle) 
		 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));

	dev_info(adev->dev, "  UVD_CONTEXT_ID=0x%08X\n",

		 RREG32(mmUVD_CONTEXT_ID));

	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",

		 RREG32(mmUVD_UDEC_ADDR_CONFIG));

	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",

		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));

	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",

		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));

}



static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

+10 −0
Original line number Diff line number Diff line
@@ -277,6 +277,10 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev) 
	size = AMDGPU_UVD_HEAP_SIZE;

	WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);

	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);



	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

}



static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
@@ -947,6 +951,12 @@ static void uvd_v6_0_print_status(void *handle) 
		 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));

	dev_info(adev->dev, "  UVD_CONTEXT_ID=0x%08X\n",

		 RREG32(mmUVD_CONTEXT_ID));

	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",

		 RREG32(mmUVD_UDEC_ADDR_CONFIG));

	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",

		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));

	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",

		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));

}



static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,