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Commit 548f437e authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Clear out unneeded register address protection code 



Now that the register address protection (RAP) support has been
moved out of the generic code get rid of a few bits and pieces
of generic support that we no longer need.

Change-Id: Ic0dedbad3d507029244ba98ba1124deb980e990c
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 2fb5b735

drivers/gpu/msm/adreno-gpulist.h

+0 −18
Original line number Diff line number Diff line
@@ -194,7 +194,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v2 = { 
		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

	},
@@ -220,7 +219,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = { 
		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

	},
@@ -286,7 +284,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a505 = { 
		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xfffffffe,

		.bus_width = 16,

	},
@@ -306,7 +303,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a506 = { 
		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xfffffffe,

		.bus_width = 16,

	},
@@ -384,7 +380,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a510 = { 
		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_256K,

		.num_protected_regs = 0x20,

		.busy_mask = 0xfffffffe,

		.bus_width = 16,

	},
@@ -510,7 +505,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a540v2 = { 
		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

	},
@@ -593,7 +587,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a512 = { 
		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_256K + SZ_16K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

	},
@@ -612,7 +605,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a508 = { 
		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

	},
@@ -786,7 +778,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = { 
		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

	},
@@ -886,7 +877,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = { 
		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.num_protected_regs = 0x20,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

	},
@@ -914,7 +904,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = { 
		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.num_protected_regs = 0x20,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

	},
@@ -1041,7 +1030,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = { 
		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0,

		.gmem_size = SZ_512K,

		.num_protected_regs = 0x30,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

	},
@@ -1131,7 +1119,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = { 
		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M, //Verified 1MB

		.num_protected_regs = 0x20,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

	},
@@ -1211,7 +1198,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = { 
		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */

		.num_protected_regs = 0x30,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

	},
@@ -1239,7 +1225,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = { 
		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */

		.num_protected_regs = 0x30,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

	},
@@ -1265,7 +1250,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = { 
		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_2M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

	},
@@ -1342,7 +1326,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = { 
		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_4K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

	},
@@ -1368,7 +1351,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = { 
		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.num_protected_regs = 0x20,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

	},

drivers/gpu/msm/adreno.h

+0 −2
Original line number Diff line number Diff line
@@ -350,7 +350,6 @@ struct adreno_reglist { 
 * @gpudev: Pointer to the GPU family specific functions for this core

 * @gmem_base: Base address of binning memory (GMEM/OCMEM)

 * @gmem_size: Amount of binning memory (GMEM/OCMEM) to reserve for the core

 * @num_protected_regs: number of protected registers

 * @busy_mask: mask to check if GPU is busy in RBBM_STATUS

 * @bus_width: Bytes transferred in 1 cycle

 */
@@ -361,7 +360,6 @@ struct adreno_gpu_core { 
	struct adreno_gpudev *gpudev;

	unsigned long gmem_base;

	size_t gmem_size;

	unsigned int num_protected_regs;

	unsigned int busy_mask;

	u32 bus_width;

};

drivers/gpu/msm/kgsl.h

+0 −10
Original line number Diff line number Diff line
@@ -332,16 +332,6 @@ struct kgsl_event_group { 
	void *priv;

};



/**

 * struct kgsl_protected_registers - Protected register range

 * @base: Offset of the range to be protected

 * @range: Range (# of registers = 2 ** range)

 */

struct kgsl_protected_registers {

	unsigned int base;

	int range;

};



/**

 * struct sparse_bind_object - Bind metadata

 * @node: Node for the rb tree

drivers/gpu/msm/kgsl_iommu.c

+0 −18
Original line number Diff line number Diff line
@@ -2152,14 +2152,6 @@ static int kgsl_iommu_set_pf_policy(struct kgsl_mmu *mmu, 
	return 0;

}



static struct kgsl_protected_registers *

kgsl_iommu_get_prot_regs(struct kgsl_mmu *mmu)

{

	struct kgsl_iommu *iommu = _IOMMU_PRIV(mmu);



	return &iommu->protect;

}



static struct kgsl_iommu_addr_entry *_find_gpuaddr(

		struct kgsl_pagetable *pagetable, uint64_t gpuaddr)

{
@@ -2611,15 +2603,6 @@ static int _kgsl_iommu_probe(struct kgsl_device *device, 
	iommu->regstart = reg_val[0];

	iommu->regsize = reg_val[1];



	/* Protecting the SMMU registers is mandatory */

	if (of_property_read_u32_array(node, "qcom,protect", reg_val, 2)) {

		dev_err(device->dev,

			"dt: no iommu protection range specified\n");

		return -EINVAL;

	}

	iommu->protect.base = reg_val[0] / sizeof(u32);

	iommu->protect.range = reg_val[1] / sizeof(u32);



	of_property_for_each_string(node, "clock-names", prop, cname) {

		struct clk *c = devm_clk_get(&pdev->dev, cname);
@@ -2707,7 +2690,6 @@ struct kgsl_mmu_ops kgsl_iommu_ops = { 
	.mmu_pt_equal = kgsl_iommu_pt_equal,

	.mmu_set_pf_policy = kgsl_iommu_set_pf_policy,

	.mmu_pagefault_resume = kgsl_iommu_pagefault_resume,

	.mmu_get_prot_regs = kgsl_iommu_get_prot_regs,

	.mmu_init_pt = kgsl_iommu_init_pt,

	.mmu_add_global = kgsl_iommu_add_global,

	.mmu_remove_global = kgsl_iommu_remove_global,

drivers/gpu/msm/kgsl_iommu.h

+0 −2
Original line number Diff line number Diff line
@@ -112,7 +112,6 @@ struct kgsl_iommu_context { 
 * @clk_enable_count: The ref count of clock enable calls

 * @clks: Array of pointers to IOMMU clocks

 * @smmu_info: smmu info used in a5xx preemption

 * @protect: register protection settings for the iommu.

 */

struct kgsl_iommu {

	struct kgsl_iommu_context ctx[KGSL_IOMMU_CONTEXT_MAX];
@@ -123,7 +122,6 @@ struct kgsl_iommu { 
	atomic_t clk_enable_count;

	struct clk *clks[KGSL_IOMMU_MAX_CLKS];

	struct kgsl_memdesc smmu_info;

	struct kgsl_protected_registers protect;

};



/*