Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 54792dc2 authored by Sakthivel K's avatar Sakthivel K Committed by James Bottomley
Browse files

[SCSI] pm80xx: SPC new firmware changes for device id 0x8081 alone 



Additional bar shift for new SPC firmware, applicable to device
id 0x8081 only.

Signed-off-by: default avatarSakthivel K <Sakthivel.SaravananKamalRaju@pmcs.com>
Signed-off-by: default avatarAnand Kumar S <AnandKumar.Santhanam@pmcs.com>
Acked-by: default avatarJack Wang <jack_wang@usish.com>
Reviewed-by: default avatarHannes Reinecke <hare@suse.de>
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent f5860992

drivers/scsi/pm8001/pm8001_hwi.c

+28 −3
Original line number Diff line number Diff line
@@ -640,6 +640,18 @@ static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 
static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)

{

	u8 i = 0;

	u16 deviceid;

	pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);

	/* 8081 controllers need BAR shift to access MPI space

	* as this is shared with BIOS data */

	if (deviceid == 0x8081) {

		if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {

			PM8001_FAIL_DBG(pm8001_ha,

				pm8001_printk("Shift Bar4 to 0x%x failed\n",

					GSM_SM_BASE));

			return -1;

		}

	}

	/* check the firmware status */

	if (-1 == check_fw_ready(pm8001_ha)) {

		PM8001_FAIL_DBG(pm8001_ha,
@@ -660,9 +672,12 @@ static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha) 
		update_inbnd_queue_table(pm8001_ha, i);

	for (i = 0; i < PM8001_MAX_OUTB_NUM; i++)

		update_outbnd_queue_table(pm8001_ha, i);

	/* 8081 controller donot require these operations */

	if (deviceid != 0x8081) {

		mpi_set_phys_g3_with_ssc(pm8001_ha, 0);

		/* 7->130ms, 34->500ms, 119->1.5s */

		mpi_set_open_retry_interval_reg(pm8001_ha, 119);

	}

	/* notify firmware update finished and check initialization status */

	if (0 == mpi_init_check(pm8001_ha)) {

		PM8001_INIT_DBG(pm8001_ha,
@@ -684,6 +699,16 @@ static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 
	u32 max_wait_count;

	u32 value;

	u32 gst_len_mpistate;

	u16 deviceid;

	pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);

	if (deviceid == 0x8081) {

		if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {

			PM8001_FAIL_DBG(pm8001_ha,

				pm8001_printk("Shift Bar4 to 0x%x failed\n",

					GSM_SM_BASE));

			return -1;

		}

	}

	init_pci_device_addresses(pm8001_ha);

	/* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the

	table is stop */

drivers/scsi/pm8001/pm8001_hwi.h

+2 −0
Original line number Diff line number Diff line
@@ -131,6 +131,8 @@ 
#define LINKRATE_30			(0x02 << 8)

#define LINKRATE_60			(0x04 << 8)



/* for new SPC controllers MEMBASE III is shared between BIOS and DATA */

#define GSM_SM_BASE			0x4F0000

struct mpi_msg_hdr{

	__le32	header;	/* Bits [11:0]  - Message operation code */

	/* Bits [15:12] - Message Category */