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Commit 542c3f4e authored by Joe Perches's avatar Joe Perches Committed by Jeff Kirsher
Browse files

e1000: Neaten e1000_config_dsp_after_link_change 



Separate a complicated bit of e1000_config_dsp_after_link_change
into a new static function e1000_1000Mb_check_cable_length.

Reduces indentation and adds a bit of clarity.

Signed-off-by: default avatarJoe Perches <joe@perches.com>
Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent dffcdde7

drivers/net/ethernet/intel/e1000/e1000_hw.c

+73 −83
Original line number Diff line number Diff line
@@ -5253,109 +5253,62 @@ static s32 e1000_check_downshift(struct e1000_hw *hw) 
	return E1000_SUCCESS;

}



/**

 * e1000_config_dsp_after_link_change

 * @hw: Struct containing variables accessed by shared code

 * @link_up: was link up at the time this was called

 *

 * returns: - E1000_ERR_PHY if fail to read/write the PHY

 *            E1000_SUCCESS at any other case.

 *

 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a

 * gigabit link is achieved to improve link quality.

 */



static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)

{

	s32 ret_val;

	u16 phy_data, phy_saved_data, speed, duplex, i;

static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {

	IGP01E1000_PHY_AGC_PARAM_A,

	IGP01E1000_PHY_AGC_PARAM_B,

	IGP01E1000_PHY_AGC_PARAM_C,

	IGP01E1000_PHY_AGC_PARAM_D

};

	u16 min_length, max_length;



	e_dbg("e1000_config_dsp_after_link_change");



	if (hw->phy_type != e1000_phy_igp)

		return E1000_SUCCESS;



	if (link_up) {

		ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);

		if (ret_val) {

			e_dbg("Error getting link speed and duplex\n");

			return ret_val;

		}



		if (speed == SPEED_1000) {

static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw)

{

	u16 min_length, max_length;

	u16 phy_data, i;

	s32 ret_val;



			ret_val =

			    e1000_get_cable_length(hw, &min_length,

						   &max_length);

	ret_val = e1000_get_cable_length(hw, &min_length, &max_length);

	if (ret_val)

		return ret_val;



			if ((hw->dsp_config_state == e1000_dsp_config_enabled)

			    && min_length >= e1000_igp_cable_length_50) {

	if (hw->dsp_config_state != e1000_dsp_config_enabled)

		return 0;



	if (min_length >= e1000_igp_cable_length_50) {

		for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {

					ret_val =

					    e1000_read_phy_reg(hw,

							       dsp_reg_array[i],

			ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],

						     &phy_data);

			if (ret_val)

				return ret_val;



					phy_data &=

					    ~IGP01E1000_PHY_EDAC_MU_INDEX;

			phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;



					ret_val =

					    e1000_write_phy_reg(hw,

								dsp_reg_array

								[i], phy_data);

			ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],

						      phy_data);

			if (ret_val)

				return ret_val;

		}

				hw->dsp_config_state =

				    e1000_dsp_config_activated;

			}



			if ((hw->ffe_config_state == e1000_ffe_config_enabled)

			    && (min_length < e1000_igp_cable_length_50)) {



				u16 ffe_idle_err_timeout =

				    FFE_IDLE_ERR_COUNT_TIMEOUT_20;

		hw->dsp_config_state = e1000_dsp_config_activated;

	} else {

		u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;

		u32 idle_errs = 0;



		/* clear previous idle error counts */

				ret_val =

				    e1000_read_phy_reg(hw, PHY_1000T_STATUS,

						       &phy_data);

		ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);

		if (ret_val)

			return ret_val;



		for (i = 0; i < ffe_idle_err_timeout; i++) {

			udelay(1000);

					ret_val =

					    e1000_read_phy_reg(hw,

							       PHY_1000T_STATUS,

			ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,

						     &phy_data);

			if (ret_val)

				return ret_val;



					idle_errs +=

					    (phy_data &

					     SR_1000T_IDLE_ERROR_CNT);

					if (idle_errs >

					    SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT)

					{

						hw->ffe_config_state =

						    e1000_ffe_config_active;

			idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);

			if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {

				hw->ffe_config_state = e1000_ffe_config_active;



						ret_val =

						    e1000_write_phy_reg(hw,

				ret_val = e1000_write_phy_reg(hw,

					      IGP01E1000_PHY_DSP_FFE,

					      IGP01E1000_PHY_DSP_FFE_CM_CP);

				if (ret_val)
@@ -5368,6 +5321,43 @@ static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) 
					    FFE_IDLE_ERR_COUNT_TIMEOUT_100;

		}

	}



	return 0;

}



/**

 * e1000_config_dsp_after_link_change

 * @hw: Struct containing variables accessed by shared code

 * @link_up: was link up at the time this was called

 *

 * returns: - E1000_ERR_PHY if fail to read/write the PHY

 *            E1000_SUCCESS at any other case.

 *

 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a

 * gigabit link is achieved to improve link quality.

 */



static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)

{

	s32 ret_val;

	u16 phy_data, phy_saved_data, speed, duplex, i;



	e_dbg("e1000_config_dsp_after_link_change");



	if (hw->phy_type != e1000_phy_igp)

		return E1000_SUCCESS;



	if (link_up) {

		ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);

		if (ret_val) {

			e_dbg("Error getting link speed and duplex\n");

			return ret_val;

		}



		if (speed == SPEED_1000) {

			ret_val = e1000_1000Mb_check_cable_length(hw);

			if (ret_val)

				return ret_val;

		}

	} else {

		if (hw->dsp_config_state == e1000_dsp_config_activated) {