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Commit 53f56d6e authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-soc-for-v4.11' of... 

Merge tag 'renesas-soc-for-v4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

Renesas ARM Based SoC Updates for v4.11

* Allow booting secondary CPU cores in debug mode

* tag 'renesas-soc-for-v4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

:
  ARM: shmobile: rcar-gen2: Remove unused rcar_gen2_read_mode_pins()
  ARM: shmobile: r8a7791: Allow booting secondary CPU cores in debug mode
  ARM: shmobile: apmu: Allow booting secondary CPU cores in debug mode
  ARM: shmobile: apmu: Add debug resource reset for secondary CPU boot
  ARM: shmobile: apmu: Add more register documentation

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents a121103c 70def3e5

arch/arm/mach-shmobile/platsmp-apmu.c

+24 −17
Original line number Diff line number Diff line
@@ -31,9 +31,21 @@ static struct { 
	int bit;

} apmu_cpus[NR_CPUS];



#define WUPCR_OFFS 0x10

#define PSTR_OFFS 0x40

#define WUPCR_OFFS	 0x10		/* Wake Up Control Register */

#define PSTR_OFFS	 0x40		/* Power Status Register */

#define CPUNCR_OFFS(n)	(0x100 + (0x10 * (n)))

					/* CPUn Power Status Control Register */

#define DBGRCR_OFFS	0x180		/* Debug Resource Reset Control Reg. */



/* Power Status Register */

#define CPUNST(r, n)	(((r) >> (n * 4)) & 3)	/* CPUn Status Bit */

#define CPUST_RUN	0		/* Run Mode */

#define CPUST_STANDBY	3		/* CoreStandby Mode */



/* Debug Resource Reset Control Register */

#define DBGCPUREN	BIT(24)		/* CPU Other Reset Request Enable */

#define DBGCPUNREN(n)	BIT((n) + 20)	/* CPUn Reset Request Enable */

#define DBGCPUPREN	BIT(19)		/* CPU Peripheral Reset Req. Enable */



static int __maybe_unused apmu_power_on(void __iomem *p, int bit)

{
@@ -59,7 +71,7 @@ static int __maybe_unused apmu_power_off_poll(void __iomem *p, int bit) 
	int k;



	for (k = 0; k < 1000; k++) {

		if (((readl_relaxed(p + PSTR_OFFS) >> (bit * 4)) & 0x03) == 3)

		if (CPUNST(readl_relaxed(p + PSTR_OFFS), bit) == CPUST_STANDBY)

			return 1;



		mdelay(1);
@@ -78,6 +90,8 @@ static int __maybe_unused apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu) 
#ifdef CONFIG_SMP

static void apmu_init_cpu(struct resource *res, int cpu, int bit)

{

	u32 x;



	if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem)

		return;
@@ -85,6 +99,11 @@ static void apmu_init_cpu(struct resource *res, int cpu, int bit) 
	apmu_cpus[cpu].bit = bit;



	pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res);



	/* Setup for debug mode */

	x = readl(apmu_cpus[cpu].iomem + DBGRCR_OFFS);

	x |= DBGCPUREN | DBGCPUNREN(bit) | DBGCPUPREN;

	writel(x, apmu_cpus[cpu].iomem + DBGRCR_OFFS);

}



static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit),
@@ -197,21 +216,9 @@ static void __init shmobile_smp_apmu_prepare_cpus_dt(unsigned int max_cpus) 
	rcar_gen2_pm_init();

}



static int shmobile_smp_apmu_boot_secondary_md21(unsigned int cpu,

						 struct task_struct *idle)

{

	/* Error out when hardware debug mode is enabled */

	if (rcar_gen2_read_mode_pins() & BIT(21)) {

		pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu);

		return -ENOTSUPP;

	}



	return shmobile_smp_apmu_boot_secondary(cpu, idle);

}



static struct smp_operations apmu_smp_ops __initdata = {

	.smp_prepare_cpus	= shmobile_smp_apmu_prepare_cpus_dt,

	.smp_boot_secondary	= shmobile_smp_apmu_boot_secondary_md21,

	.smp_boot_secondary	= shmobile_smp_apmu_boot_secondary,

#ifdef CONFIG_HOTPLUG_CPU

	.cpu_can_disable	= shmobile_smp_cpu_can_disable,

	.cpu_die		= shmobile_smp_apmu_cpu_die,

arch/arm/mach-shmobile/rcar-gen2.h

+0 −2
Original line number Diff line number Diff line
@@ -2,8 +2,6 @@ 
#define __ASM_RCAR_GEN2_H__



void rcar_gen2_timer_init(void);

#define MD(nr) BIT(nr)

u32 rcar_gen2_read_mode_pins(void);

void rcar_gen2_reserve(void);

void rcar_gen2_pm_init(void);

arch/arm/mach-shmobile/setup-rcar-gen2.c

+0 −18
Original line number Diff line number Diff line
@@ -29,24 +29,6 @@ 
#include "common.h"

#include "rcar-gen2.h"



#define MODEMR 0xe6160060



u32 rcar_gen2_read_mode_pins(void)

{

	static u32 mode;

	static bool mode_valid;



	if (!mode_valid) {

		void __iomem *modemr = ioremap_nocache(MODEMR, 4);

		BUG_ON(!modemr);

		mode = ioread32(modemr);

		iounmap(modemr);

		mode_valid = true;

	}



	return mode;

}



static unsigned int __init get_extal_freq(void)

{

	struct device_node *cpg, *extal;

arch/arm/mach-shmobile/smp-r8a7791.c

+1 −13
Original line number Diff line number Diff line
@@ -42,21 +42,9 @@ static void __init r8a7791_smp_prepare_cpus(unsigned int max_cpus) 
	rcar_gen2_pm_init();

}



static int r8a7791_smp_boot_secondary(unsigned int cpu,

				      struct task_struct *idle)

{

	/* Error out when hardware debug mode is enabled */

	if (rcar_gen2_read_mode_pins() & BIT(21)) {

		pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu);

		return -ENOTSUPP;

	}



	return shmobile_smp_apmu_boot_secondary(cpu, idle);

}



const struct smp_operations r8a7791_smp_ops __initconst = {

	.smp_prepare_cpus	= r8a7791_smp_prepare_cpus,

	.smp_boot_secondary	= r8a7791_smp_boot_secondary,

	.smp_boot_secondary	= shmobile_smp_apmu_boot_secondary,

#ifdef CONFIG_HOTPLUG_CPU

	.cpu_can_disable	= shmobile_smp_cpu_can_disable,

	.cpu_die		= shmobile_smp_apmu_cpu_die,