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Commit 53c7972d authored by Thierry Reding's avatar Thierry Reding
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pwm: tiecap: Miscellaneous coding style fixups 



I noticed most of these while reviewing another patch and thought I'd
fix them while at it. These are mostly changes to make variable types
more strict and whitespace fixups.

Signed-off-by: default avatarThierry Reding <thierry.reding@gmail.com>
parent 999f6f71

drivers/pwm/pwm-tiecap.c

+47 −41
Original line number Diff line number Diff line
@@ -64,9 +64,9 @@ static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 
		int duty_ns, int period_ns)

{

	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);

	u32 period_cycles, duty_cycles;

	unsigned long long c;

	unsigned long period_cycles, duty_cycles;

	unsigned int reg_val;

	u16 value;



	if (period_ns > NSEC_PER_SEC)

		return -ERANGE;
@@ -74,7 +74,7 @@ static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 
	c = pc->clk_rate;

	c = c * period_ns;

	do_div(c, NSEC_PER_SEC);

	period_cycles = (unsigned long)c;

	period_cycles = (u32)c;



	if (period_cycles < 1) {

		period_cycles = 1;
@@ -83,17 +83,17 @@ static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 
		c = pc->clk_rate;

		c = c * duty_ns;

		do_div(c, NSEC_PER_SEC);

		duty_cycles = (unsigned long)c;

		duty_cycles = (u32)c;

	}



	pm_runtime_get_sync(pc->chip.dev);



	reg_val = readw(pc->mmio_base + ECCTL2);

	value = readw(pc->mmio_base + ECCTL2);



	/* Configure APWM mode & disable sync option */

	reg_val |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;

	value |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;



	writew(reg_val, pc->mmio_base + ECCTL2);

	writew(value, pc->mmio_base + ECCTL2);



	if (!pwm_is_enabled(pwm)) {

		/* Update active registers if not running */
@@ -110,13 +110,14 @@ static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 
	}



	if (!pwm_is_enabled(pwm)) {

		reg_val = readw(pc->mmio_base + ECCTL2);

		value = readw(pc->mmio_base + ECCTL2);

		/* Disable APWM mode to put APWM output Low */

		reg_val &= ~ECCTL2_APWM_MODE;

		writew(reg_val, pc->mmio_base + ECCTL2);

		value &= ~ECCTL2_APWM_MODE;

		writew(value, pc->mmio_base + ECCTL2);

	}



	pm_runtime_put_sync(pc->chip.dev);



	return 0;

}
@@ -124,26 +125,30 @@ static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, 
				 enum pwm_polarity polarity)

{

	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);

	unsigned short reg_val;

	u16 value;



	pm_runtime_get_sync(pc->chip.dev);

	reg_val = readw(pc->mmio_base + ECCTL2);



	value = readw(pc->mmio_base + ECCTL2);



	if (polarity == PWM_POLARITY_INVERSED)

		/* Duty cycle defines LOW period of PWM */

		reg_val |= ECCTL2_APWM_POL_LOW;

		value |= ECCTL2_APWM_POL_LOW;

	else

		/* Duty cycle defines HIGH period of PWM */

		reg_val &= ~ECCTL2_APWM_POL_LOW;

		value &= ~ECCTL2_APWM_POL_LOW;



	writew(value, pc->mmio_base + ECCTL2);



	writew(reg_val, pc->mmio_base + ECCTL2);

	pm_runtime_put_sync(pc->chip.dev);



	return 0;

}



static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)

{

	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);

	unsigned int reg_val;

	u16 value;



	/* Leave clock enabled on enabling PWM */

	pm_runtime_get_sync(pc->chip.dev);
@@ -152,24 +157,25 @@ static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 
	 * Enable 'Free run Time stamp counter mode' to start counter

	 * and  'APWM mode' to enable APWM output

	 */

	reg_val = readw(pc->mmio_base + ECCTL2);

	reg_val |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;

	writew(reg_val, pc->mmio_base + ECCTL2);

	value = readw(pc->mmio_base + ECCTL2);

	value |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;

	writew(value, pc->mmio_base + ECCTL2);



	return 0;

}



static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)

{

	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);

	unsigned int reg_val;

	u16 value;



	/*

	 * Disable 'Free run Time stamp counter mode' to stop counter

	 * and 'APWM mode' to put APWM output to low

	 */

	reg_val = readw(pc->mmio_base + ECCTL2);

	reg_val &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);

	writew(reg_val, pc->mmio_base + ECCTL2);

	value = readw(pc->mmio_base + ECCTL2);

	value &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);

	writew(value, pc->mmio_base + ECCTL2);



	/* Disable clock on PWM disable */

	pm_runtime_put_sync(pc->chip.dev);
@@ -202,10 +208,10 @@ MODULE_DEVICE_TABLE(of, ecap_of_match); 
static int ecap_pwm_probe(struct platform_device *pdev)

{

	struct device_node *np = pdev->dev.of_node;

	int ret;

	struct ecap_pwm_chip *pc;

	struct resource *r;

	struct clk *clk;

	struct ecap_pwm_chip *pc;

	int ret;



	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);

	if (!pc)
@@ -259,6 +265,7 @@ static int ecap_pwm_remove(struct platform_device *pdev) 
	struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);



	pm_runtime_disable(&pdev->dev);



	return pwmchip_remove(&pc->chip);

}
@@ -318,7 +325,6 @@ static struct platform_driver ecap_pwm_driver = { 
	.probe = ecap_pwm_probe,

	.remove = ecap_pwm_remove,

};



module_platform_driver(ecap_pwm_driver);



MODULE_DESCRIPTION("ECAP PWM driver");