Merge "ARM: dts: msm: add CWB/LUTDMA VBIF remap setting for kona target" (53c5b113) · Commits · e / devices / android_kernel_oneplus_sm7250

Documentation/devicetree/bindings/display/msm/sde.txt

+20 −0

Original line number	Diff line number	Diff line
		@@ -312,6 +312,13 @@ Optional properties:
		defined in reg property.
		- qcom,sde-reg-dma-broadcast-disabled: Boolean property to indicate if broadcast
		functionality in the register dma hardware block should be used.
		- qcom,sde-reg-dma-xin-id: VBIF clients id (xin) corresponding
		to the LUTDMA block.
		- qcom,sde-reg-dma-clk-ctrl: Array of 2 cell property describing clk control
		offsets for dynamic clock gating. 1st value
		in the array represents offset of the control
		register. 2nd value represents bit offset within
		control register.
		- qcom,sde-dram-channels: This represents the number of channels in the
		Bus memory controller.
		- qcom,sde-num-nrt-paths: Integer property represents the number of non-realtime
		@@ -371,6 +378,10 @@ Optional properties:
		priority for realtime clients.
		- qcom,sde-vbif-qos-nrt-remap: This array is used to program vbif qos remapper register
		priority for non-realtime clients.
		- qcom,sde-vbif-qos-cwb-remap: This array is used to program vbif qos remapper register
		priority for concurrent writeback clients.
		- qcom,sde-vbif-qos-lutdma-remap: This array is used to program vbif qos remapper register
		priority for lutdma client.
		- qcom,sde-danger-lut: Array of 5 cell property, with a format of
		<linear, tile, nrt, cwb, tile-qseed>,
		indicating the danger luts on sspp.
		@@ -733,6 +744,15 @@ Example:

		qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
		qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
		qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>;
		qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>;

		qcom,sde-reg-dma-off = <0>;
		qcom,sde-reg-dma-version = <0x00010002>;
		qcom,sde-reg-dma-trigger-off = <0x119c>;
		qcom,sde-reg-dma-broadcast-disabled = <0>;
		qcom,sde-reg-dma-xin-id = <7>;
		qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;

		qcom,sde-sspp-vig-blocks {
		qcom,sde-vig-csc-off = <0x320>;

arch/arm64/boot/dts/qcom/kona-sde.dtsi

+5 −1

Original line number	Diff line number	Diff line
		@@ -74,7 +74,7 @@
		qcom,sde-wb-size = <0x2c8>;
		qcom,sde-wb-xin-id = <6>;
		qcom,sde-wb-id = <2>;
		qcom,sde-wb-clk-ctrl = <0x3b8 24>;
		qcom,sde-wb-clk-ctrl = <0x2bc 16>;

		qcom,sde-intf-off = <0x6b000 0x6b800
		0x6c000 0x6c800>;
		@@ -177,6 +177,8 @@

		qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
		qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
		qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>;
		qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>;

		/* macrotile & macrotile-qseed has the same configs */
		qcom,sde-danger-lut = <0x0000000f 0x0000ffff
		@@ -205,6 +207,8 @@
		qcom,sde-reg-dma-off = <0>;
		qcom,sde-reg-dma-version = <0x00010002>;
		qcom,sde-reg-dma-trigger-off = <0x119c>;
		qcom,sde-reg-dma-xin-id = <7>;
		qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;

		qcom,sde-secure-sid-mask = <0x4200801>;

drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c

+4 −3

Original line number	Diff line number	Diff line
		@@ -139,12 +139,13 @@ static void sde_encoder_phys_wb_set_qos_remap(
		qos_params.xin_id = hw_wb->caps->xin_id;
		qos_params.clk_ctrl = hw_wb->caps->clk_ctrl;
		qos_params.num = hw_wb->idx - WB_0;
		qos_params.is_rt = sde_crtc_get_client_type(crtc) != NRT_CLIENT;
		qos_params.client_type = phys_enc->in_clone_mode ?
		VBIF_CWB_CLIENT : VBIF_NRT_CLIENT;

		SDE_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d rt:%d\n",
		SDE_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d rt:%d clone:%d\n",
		qos_params.num,
		qos_params.vbif_idx,
		qos_params.xin_id, qos_params.is_rt);
		qos_params.xin_id, qos_params.client_type);

		sde_vbif_set_qos_remap(phys_enc->sde_kms, &qos_params);
		}

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+109 −94

Original line number	Diff line number	Diff line
		@@ -379,10 +379,12 @@ enum {
		VBIF_DEFAULT_OT_WR_LIMIT,
		VBIF_DYNAMIC_OT_RD_LIMIT,
		VBIF_DYNAMIC_OT_WR_LIMIT,
		VBIF_QOS_RT_REMAP,
		VBIF_QOS_NRT_REMAP,
		VBIF_MEMTYPE_0,
		VBIF_MEMTYPE_1,
		VBIF_QOS_RT_REMAP,
		VBIF_QOS_NRT_REMAP,
		VBIF_QOS_CWB_REMAP,
		VBIF_QOS_LUTDMA_REMAP,
		VBIF_PROP_MAX,
		};

		@@ -397,6 +399,8 @@ enum {
		REG_DMA_VERSION,
		REG_DMA_TRIGGER_OFF,
		REG_DMA_BROADCAST_DISABLED,
		REG_DMA_XIN_ID,
		REG_DMA_CLK_CTRL,
		REG_DMA_PROP_MAX
		};

		@@ -698,12 +702,16 @@ static struct sde_prop_type vbif_prop[] = {
		PROP_TYPE_U32_ARRAY},
		{VBIF_DYNAMIC_OT_WR_LIMIT, "qcom,sde-vbif-dynamic-ot-wr-limit", false,
		PROP_TYPE_U32_ARRAY},
		{VBIF_MEMTYPE_0, "qcom,sde-vbif-memtype-0", false, PROP_TYPE_U32_ARRAY},
		{VBIF_MEMTYPE_1, "qcom,sde-vbif-memtype-1", false, PROP_TYPE_U32_ARRAY},
		{VBIF_QOS_RT_REMAP, "qcom,sde-vbif-qos-rt-remap", false,
		PROP_TYPE_U32_ARRAY},
		{VBIF_QOS_NRT_REMAP, "qcom,sde-vbif-qos-nrt-remap", false,
		PROP_TYPE_U32_ARRAY},
		{VBIF_MEMTYPE_0, "qcom,sde-vbif-memtype-0", false, PROP_TYPE_U32_ARRAY},
		{VBIF_MEMTYPE_1, "qcom,sde-vbif-memtype-1", false, PROP_TYPE_U32_ARRAY},
		{VBIF_QOS_CWB_REMAP, "qcom,sde-vbif-qos-cwb-remap", false,
		PROP_TYPE_U32_ARRAY},
		{VBIF_QOS_LUTDMA_REMAP, "qcom,sde-vbif-qos-lutdma-remap", false,
		PROP_TYPE_U32_ARRAY},
		};

		static struct sde_prop_type uidle_prop[] = {
		@@ -721,6 +729,10 @@ static struct sde_prop_type reg_dma_prop[REG_DMA_PROP_MAX] = {
		PROP_TYPE_U32},
		[REG_DMA_BROADCAST_DISABLED] = {REG_DMA_BROADCAST_DISABLED,
		"qcom,sde-reg-dma-broadcast-disabled", false, PROP_TYPE_BOOL},
		[REG_DMA_XIN_ID] = {REG_DMA_XIN_ID,
		"qcom,sde-reg-dma-xin-id", false, PROP_TYPE_U32},
		[REG_DMA_CLK_CTRL] = {REG_DMA_XIN_ID,
		"qcom,sde-reg-dma-clk-ctrl", false, PROP_TYPE_BIT_OFFSET_ARRAY},
		};

		static struct sde_prop_type merge_3d_prop[] = {
		@@ -2692,60 +2704,40 @@ static int _sde_vbif_populate_qos_parsing(struct sde_mdss_cfg *sde_cfg,
		struct sde_vbif_cfg vbif, struct sde_prop_value prop_value,
		int *prop_count)
		{
		int j;

		vbif->qos_rt_tbl.npriority_lvl =
		prop_count[VBIF_QOS_RT_REMAP];
		SDE_DEBUG("qos_rt_tbl.npriority_lvl=%u\n",
		vbif->qos_rt_tbl.npriority_lvl);
		if (vbif->qos_rt_tbl.npriority_lvl == sde_cfg->vbif_qos_nlvl) {
		vbif->qos_rt_tbl.priority_lvl = kcalloc(
		vbif->qos_rt_tbl.npriority_lvl, sizeof(u32),
		GFP_KERNEL);
		if (!vbif->qos_rt_tbl.priority_lvl)
		return -ENOMEM;
		} else if (vbif->qos_rt_tbl.npriority_lvl) {
		vbif->qos_rt_tbl.npriority_lvl = 0;
		vbif->qos_rt_tbl.priority_lvl = NULL;
		SDE_ERROR("invalid qos rt table\n");
		}

		for (j = 0; j < vbif->qos_rt_tbl.npriority_lvl; j++) {
		vbif->qos_rt_tbl.priority_lvl[j] =
		PROP_VALUE_ACCESS(prop_value,
		VBIF_QOS_RT_REMAP, j);
		SDE_DEBUG("lvl[%d]=%u\n", j,
		vbif->qos_rt_tbl.priority_lvl[j]);
		}

		vbif->qos_nrt_tbl.npriority_lvl =
		prop_count[VBIF_QOS_NRT_REMAP];
		SDE_DEBUG("qos_nrt_tbl.npriority_lvl=%u\n",
		vbif->qos_nrt_tbl.npriority_lvl);

		if (vbif->qos_nrt_tbl.npriority_lvl == sde_cfg->vbif_qos_nlvl) {
		vbif->qos_nrt_tbl.priority_lvl = kcalloc(
		vbif->qos_nrt_tbl.npriority_lvl, sizeof(u32),
		GFP_KERNEL);
		if (!vbif->qos_nrt_tbl.priority_lvl)
		int i, j;
		int prop_index = VBIF_QOS_RT_REMAP;

		for (i = VBIF_RT_CLIENT;
		((i < VBIF_MAX_CLIENT) && (prop_index < VBIF_PROP_MAX));
		i++, prop_index++) {
		vbif->qos_tbl[i].npriority_lvl = prop_count[prop_index];
		SDE_DEBUG("qos_tbl[%d].npriority_lvl=%u\n",
		i, vbif->qos_tbl[i].npriority_lvl);

		if (vbif->qos_tbl[i].npriority_lvl == sde_cfg->vbif_qos_nlvl) {
		vbif->qos_tbl[i].priority_lvl = kcalloc(
		vbif->qos_tbl[i].npriority_lvl,
		sizeof(u32), GFP_KERNEL);
		if (!vbif->qos_tbl[i].priority_lvl)
		return -ENOMEM;
		} else if (vbif->qos_nrt_tbl.npriority_lvl) {
		vbif->qos_nrt_tbl.npriority_lvl = 0;
		vbif->qos_nrt_tbl.priority_lvl = NULL;
		SDE_ERROR("invalid qos nrt table\n");
		} else if (vbif->qos_tbl[i].npriority_lvl) {
		vbif->qos_tbl[i].npriority_lvl = 0;
		vbif->qos_tbl[i].priority_lvl = NULL;
		SDE_ERROR("invalid qos table for client:%d, prop:%d\n",
		i, prop_index);
		}

		for (j = 0; j < vbif->qos_nrt_tbl.npriority_lvl; j++) {
		vbif->qos_nrt_tbl.priority_lvl[j] =
		PROP_VALUE_ACCESS(prop_value,
		VBIF_QOS_NRT_REMAP, j);
		SDE_DEBUG("lvl[%d]=%u\n", j,
		vbif->qos_nrt_tbl.priority_lvl[j]);
		for (j = 0; j < vbif->qos_tbl[i].npriority_lvl; j++) {
		vbif->qos_tbl[i].priority_lvl[j] =
		PROP_VALUE_ACCESS(prop_value, prop_index, j);
		SDE_DEBUG("client:%d, prop:%d, lvl[%d]=%u\n",
		i, prop_index, j,
		vbif->qos_tbl[i].priority_lvl[j]);
		}

		if (vbif->qos_rt_tbl.npriority_lvl \|\|
		vbif->qos_nrt_tbl.npriority_lvl)
		if (vbif->qos_tbl[i].npriority_lvl)
		set_bit(SDE_VBIF_QOS_REMAP, &vbif->features);
		}

		return 0;
		}
		@@ -2829,6 +2821,16 @@ static int sde_vbif_parse_dt(struct device_node *np,
		if (rc)
		goto end;

		rc = _validate_dt_entry(np, &vbif_prop[VBIF_MEMTYPE_0], 1,
		&prop_count[VBIF_MEMTYPE_0], NULL);
		if (rc)
		goto end;

		rc = _validate_dt_entry(np, &vbif_prop[VBIF_MEMTYPE_1], 1,
		&prop_count[VBIF_MEMTYPE_1], NULL);
		if (rc)
		goto end;

		rc = _validate_dt_entry(np, &vbif_prop[VBIF_QOS_RT_REMAP], 1,
		&prop_count[VBIF_QOS_RT_REMAP], NULL);
		if (rc)
		@@ -2839,13 +2841,13 @@ static int sde_vbif_parse_dt(struct device_node *np,
		if (rc)
		goto end;

		rc = _validate_dt_entry(np, &vbif_prop[VBIF_MEMTYPE_0], 1,
		&prop_count[VBIF_MEMTYPE_0], NULL);
		rc = _validate_dt_entry(np, &vbif_prop[VBIF_QOS_CWB_REMAP], 1,
		&prop_count[VBIF_QOS_CWB_REMAP], NULL);
		if (rc)
		goto end;

		rc = _validate_dt_entry(np, &vbif_prop[VBIF_MEMTYPE_1], 1,
		&prop_count[VBIF_MEMTYPE_1], NULL);
		rc = _validate_dt_entry(np, &vbif_prop[VBIF_QOS_LUTDMA_REMAP], 1,
		&prop_count[VBIF_QOS_LUTDMA_REMAP], NULL);
		if (rc)
		goto end;

		@@ -3152,40 +3154,52 @@ static int sde_top_parse_dt(struct device_node np, struct sde_mdss_cfg cfg)
		static int sde_parse_reg_dma_dt(struct device_node *np,
		struct sde_mdss_cfg *sde_cfg)
		{
		u32 val;
		int rc = 0;
		int i = 0;
		int rc = 0, i, prop_count[REG_DMA_PROP_MAX];
		struct sde_prop_value *prop_value = NULL;
		u32 off_count;
		bool prop_exists[REG_DMA_PROP_MAX];

		sde_cfg->reg_dma_count = 0;
		for (i = 0; i < REG_DMA_PROP_MAX; i++) {
		if (reg_dma_prop[i].type == PROP_TYPE_BOOL) {
		val = of_property_read_bool(np,
		reg_dma_prop[i].prop_name);
		} else {
		rc = of_property_read_u32(np, reg_dma_prop[i].prop_name,
		&val);
		if (rc)
		break;
		}
		switch (i) {
		case REG_DMA_OFF:
		sde_cfg->dma_cfg.base = val;
		break;
		case REG_DMA_VERSION:
		sde_cfg->dma_cfg.version = val;
		break;
		case REG_DMA_TRIGGER_OFF:
		sde_cfg->dma_cfg.trigger_sel_off = val;
		break;
		case REG_DMA_BROADCAST_DISABLED:
		sde_cfg->dma_cfg.broadcast_disabled = val;
		break;
		default:
		break;
		prop_value = kcalloc(REG_DMA_PROP_MAX,
		sizeof(struct sde_prop_value), GFP_KERNEL);
		if (!prop_value) {
		rc = -ENOMEM;
		goto end;
		}

		rc = _validate_dt_entry(np, reg_dma_prop, ARRAY_SIZE(reg_dma_prop),
		prop_count, &off_count);
		if (rc \|\| !off_count)
		goto end;

		rc = _read_dt_entry(np, reg_dma_prop, ARRAY_SIZE(reg_dma_prop),
		prop_count, prop_exists, prop_value);
		if (rc)
		goto end;

		sde_cfg->reg_dma_count = off_count;
		sde_cfg->dma_cfg.base = PROP_VALUE_ACCESS(prop_value, REG_DMA_OFF, 0);
		sde_cfg->dma_cfg.version = PROP_VALUE_ACCESS(prop_value,
		REG_DMA_VERSION, 0);
		sde_cfg->dma_cfg.trigger_sel_off = PROP_VALUE_ACCESS(prop_value,
		REG_DMA_TRIGGER_OFF, 0);
		sde_cfg->dma_cfg.broadcast_disabled = PROP_VALUE_ACCESS(prop_value,
		REG_DMA_BROADCAST_DISABLED, 0);
		sde_cfg->dma_cfg.xin_id = PROP_VALUE_ACCESS(prop_value,
		REG_DMA_XIN_ID, 0);
		sde_cfg->dma_cfg.clk_ctrl = SDE_CLK_CTRL_LUTDMA;
		sde_cfg->dma_cfg.vbif_idx = VBIF_RT;

		for (i = 0; i < sde_cfg->mdp_count; i++) {
		sde_cfg->mdp[i].clk_ctrls[sde_cfg->dma_cfg.clk_ctrl].reg_off =
		PROP_BITVALUE_ACCESS(prop_value,
		REG_DMA_CLK_CTRL, 0, 0);
		sde_cfg->mdp[i].clk_ctrls[sde_cfg->dma_cfg.clk_ctrl].bit_off =
		PROP_BITVALUE_ACCESS(prop_value,
		REG_DMA_CLK_CTRL, 0, 1);
		}
		if (!rc && i == REG_DMA_PROP_MAX)
		sde_cfg->reg_dma_count = 1;

		end:
		kfree(prop_value);
		/* reg dma is optional feature hence return 0 */
		return 0;
		}
		@@ -3914,7 +3928,7 @@ static int _sde_hardware_post_caps(struct sde_mdss_cfg *sde_cfg,

		void sde_hw_catalog_deinit(struct sde_mdss_cfg *sde_cfg)
		{
		int i;
		int i, j;

		if (!sde_cfg)
		return;
		@@ -3940,8 +3954,9 @@ void sde_hw_catalog_deinit(struct sde_mdss_cfg *sde_cfg)
		for (i = 0; i < sde_cfg->vbif_count; i++) {
		kfree(sde_cfg->vbif[i].dynamic_ot_rd_tbl.cfg);
		kfree(sde_cfg->vbif[i].dynamic_ot_wr_tbl.cfg);
		kfree(sde_cfg->vbif[i].qos_rt_tbl.priority_lvl);
		kfree(sde_cfg->vbif[i].qos_nrt_tbl.priority_lvl);

		for (j = VBIF_RT_CLIENT; j < VBIF_MAX_CLIENT; j++)
		kfree(sde_cfg->vbif[i].qos_tbl[j].priority_lvl);
		}

		for (i = 0; i < SDE_QOS_LUT_USAGE_MAX; i++)

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+25 −4

Original line number	Diff line number	Diff line
		@@ -705,6 +705,7 @@ enum sde_clk_ctrl_type {
		SDE_CLK_CTRL_WB0,
		SDE_CLK_CTRL_WB1,
		SDE_CLK_CTRL_WB2,
		SDE_CLK_CTRL_LUTDMA,
		SDE_CLK_CTRL_MAX,
		};

		@@ -997,6 +998,22 @@ struct sde_vbif_qos_tbl {
		u32 *priority_lvl;
		};

		/**
		* enum sde_vbif_client_type
		* @VBIF_RT_CLIENT: real time client
		* @VBIF_NRT_CLIENT: non-realtime clients like writeback
		* @VBIF_CWB_CLIENT: concurrent writeback client
		* @VBIF_LUTDMA_CLIENT: LUTDMA client
		* @VBIF_MAX_CLIENT: max number of clients
		*/
		enum sde_vbif_client_type {
		VBIF_RT_CLIENT,
		VBIF_NRT_CLIENT,
		VBIF_CWB_CLIENT,
		VBIF_LUTDMA_CLIENT,
		VBIF_MAX_CLIENT
		};

		/**
		* struct sde_vbif_cfg - information of VBIF blocks
		* @id enum identifying this block
		@@ -1007,8 +1024,7 @@ struct sde_vbif_qos_tbl {
		* @xin_halt_timeout maximum time (in usec) for xin to halt
		* @dynamic_ot_rd_tbl dynamic OT read configuration table
		* @dynamic_ot_wr_tbl dynamic OT write configuration table
		* @qos_rt_tbl real-time QoS priority table
		* @qos_nrt_tbl non-real-time QoS priority table
		* @qos_tbl Array of QoS priority table
		* @memtype_count number of defined memtypes
		* @memtype array of xin memtype definitions
		*/
		@@ -1019,8 +1035,7 @@ struct sde_vbif_cfg {
		u32 xin_halt_timeout;
		struct sde_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl;
		struct sde_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl;
		struct sde_vbif_qos_tbl qos_rt_tbl;
		struct sde_vbif_qos_tbl qos_nrt_tbl;
		struct sde_vbif_qos_tbl qos_tbl[VBIF_MAX_CLIENT];
		u32 memtype_count;
		u32 memtype[MAX_XIN_COUNT];
		};
		@@ -1032,12 +1047,18 @@ struct sde_vbif_cfg {
		* @version version of lutdma hw block
		* @trigger_sel_off offset to trigger select registers of lutdma
		* @broadcast_disabled flag indicating if broadcast usage should be avoided
		* @xin_id VBIF xin client-id for LUTDMA
		* @vbif_idx VBIF id (RT/NRT)
		* @clk_ctrl VBIF xin client clk-ctrl
		*/
		struct sde_reg_dma_cfg {
		SDE_HW_BLK_INFO;
		u32 version;
		u32 trigger_sel_off;
		u32 broadcast_disabled;
		u32 xin_id;
		u32 vbif_idx;
		enum sde_clk_ctrl_type clk_ctrl;
		};

		/**