Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 53a31b07 authored by Brian Niebuhr's avatar Brian Niebuhr Committed by Sekhar Nori
Browse files

spi: davinci: make chip-slect specific parameters really chip-select specific 



Some chip-select specific paramterers like wdelay, parity, usage of
chip-select timers (and the actual timer values) are included in
platform data forcing the same behaviour across all chip-selects.

Create a new davinci_spi_config data structure which can be passed
along using controller_data member of spi_device data structure
on a per-device basis.

Signed-off-by: default avatarBrian Niebuhr <bniebuhr@efjohnson.com>
Tested-By: default avatarMichael Williamson <michael.williamson@criticallink.com>
Signed-off-by: default avatarSekhar Nori <nsekhar@ti.com>
parent 472880c7

arch/arm/mach-davinci/dm355.c

+0 −3
Original line number Diff line number Diff line
@@ -413,10 +413,7 @@ static struct davinci_spi_platform_data dm355_spi0_pdata = { 
	.version 	= SPI_VERSION_1,

	.num_chipselect = 2,

	.clk_internal	= 1,

	.intr_level	= 0,

	.poll_mode	= 1,	/* 0 -> interrupt mode 1-> polling mode */

	.c2tdelay	= 0,

	.t2cdelay	= 0,

};

static struct platform_device dm355_spi0_device = {

	.name = "spi_davinci",

arch/arm/mach-davinci/dm365.c

+0 −3
Original line number Diff line number Diff line
@@ -626,10 +626,7 @@ static struct davinci_spi_platform_data dm365_spi0_pdata = { 
	.version 	= SPI_VERSION_1,

	.num_chipselect = 2,

	.clk_internal	= 1,

	.intr_level	= 0,

	.poll_mode	= 1,	/* 0 -> interrupt mode 1-> polling mode */

	.c2tdelay	= 0,

	.t2cdelay	= 0,

};



static struct resource dm365_spi0_resources[] = {

arch/arm/mach-davinci/include/mach/spi.h

+8 −5
Original line number Diff line number Diff line
@@ -29,17 +29,20 @@ enum { 
struct davinci_spi_platform_data {

	u8	version;

	u8	num_chipselect;

	u8	wdelay;

	u8	odd_parity;

	u8	parity_enable;

	u8	timer_disable;

	u8	clk_internal;

	u8	intr_level;

	u8	poll_mode;

	u8	use_dma;

	u8	*chip_sel;

};



struct davinci_spi_config {

	u8	wdelay;

	u8	odd_parity;

	u8	parity_enable;

	u8	timer_disable;

	u8	c2tdelay;

	u8	t2cdelay;

	u8	*chip_sel;

};



#endif	/* __ARCH_ARM_DAVINCI_SPI_H */

drivers/spi/davinci_spi.c

+37 −30
Original line number Diff line number Diff line
@@ -156,6 +156,8 @@ struct davinci_spi { 
	struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT];

};



static struct davinci_spi_config davinci_spi_default_cfg;



static unsigned use_dma;



static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi)
@@ -434,8 +436,12 @@ static int davinci_spi_setup(struct spi_device *spi) 
	int retval;

	struct davinci_spi *davinci_spi;

	struct davinci_spi_dma *davinci_spi_dma;

	struct davinci_spi_config *spicfg;



	davinci_spi = spi_master_get_devdata(spi->master);

	spicfg = (struct davinci_spi_config *)spi->controller_data;

	if (!spicfg)

		spicfg = &davinci_spi_default_cfg;



	/* if bits per word length is zero then set it default 8 */

	if (!spi->bits_per_word)
@@ -496,49 +502,44 @@ static int davinci_spi_setup(struct spi_device *spi) 
	 */



	if (davinci_spi->version == SPI_VERSION_2) {



		clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK,

							spi->chip_select);

		set_fmt_bits(davinci_spi->base,

				(davinci_spi->pdata->wdelay

						<< SPIFMT_WDELAY_SHIFT)

					& SPIFMT_WDELAY_MASK,

				spi->chip_select);

				(spicfg->wdelay << SPIFMT_WDELAY_SHIFT) &

				SPIFMT_WDELAY_MASK, spi->chip_select);



		if (davinci_spi->pdata->odd_parity)

			set_fmt_bits(davinci_spi->base,

					SPIFMT_ODD_PARITY_MASK,

		if (spicfg->odd_parity)

			set_fmt_bits(davinci_spi->base, SPIFMT_ODD_PARITY_MASK,

							spi->chip_select);

		else

			clear_fmt_bits(davinci_spi->base,

					SPIFMT_ODD_PARITY_MASK,

					spi->chip_select);



		if (davinci_spi->pdata->parity_enable)

			set_fmt_bits(davinci_spi->base,

					SPIFMT_PARITYENA_MASK,

		if (spicfg->parity_enable)

			set_fmt_bits(davinci_spi->base, SPIFMT_PARITYENA_MASK,

							spi->chip_select);

		else

			clear_fmt_bits(davinci_spi->base,

					SPIFMT_PARITYENA_MASK,

			clear_fmt_bits(davinci_spi->base, SPIFMT_PARITYENA_MASK,

							spi->chip_select);



		if (spi->mode & SPI_READY)

			set_fmt_bits(davinci_spi->base,

					SPIFMT_WAITENA_MASK,

		if (spicfg->timer_disable)

			set_fmt_bits(davinci_spi->base, SPIFMT_DISTIMER_MASK,

							spi->chip_select);

		else

			clear_fmt_bits(davinci_spi->base,

					SPIFMT_WAITENA_MASK,

			clear_fmt_bits(davinci_spi->base, SPIFMT_DISTIMER_MASK,

							spi->chip_select);



		if (davinci_spi->pdata->timer_disable)

		if (spi->mode & SPI_READY)

			set_fmt_bits(davinci_spi->base,

					SPIFMT_DISTIMER_MASK,

					SPIFMT_WAITENA_MASK,

					spi->chip_select);

		else

			clear_fmt_bits(davinci_spi->base,

					SPIFMT_DISTIMER_MASK,

					SPIFMT_WAITENA_MASK,

					spi->chip_select);



	}



	retval = davinci_spi_setup_transfer(spi, NULL);
@@ -662,9 +663,13 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t) 
	u32 tx_data, data1_reg_val;

	u32 buf_val, flg_val;

	struct davinci_spi_platform_data *pdata;

	struct davinci_spi_config *spicfg;



	davinci_spi = spi_master_get_devdata(spi->master);

	pdata = davinci_spi->pdata;

	spicfg = (struct davinci_spi_config *)spi->controller_data;

	if (!spicfg)

		spicfg = &davinci_spi_default_cfg;



	davinci_spi->tx = t->tx_buf;

	davinci_spi->rx = t->rx_buf;
@@ -684,8 +689,8 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t) 
	/* Enable SPI */

	set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);



	iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |

			(pdata->t2cdelay << SPI_T2CDELAY_SHIFT),

	iowrite32((spicfg->c2tdelay << SPI_C2TDELAY_SHIFT) |

			(spicfg->t2cdelay << SPI_T2CDELAY_SHIFT),

			davinci_spi->base + SPIDELAY);



	count = davinci_spi->count;
@@ -792,12 +797,14 @@ static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t) 
	struct davinci_spi_dma *davinci_spi_dma;

	int word_len, data_type, ret;

	unsigned long tx_reg, rx_reg;

	struct davinci_spi_platform_data *pdata;

	struct davinci_spi_config *spicfg;

	struct device *sdev;



	davinci_spi = spi_master_get_devdata(spi->master);

	pdata = davinci_spi->pdata;

	sdev = davinci_spi->bitbang.master->dev.parent;

	spicfg = (struct davinci_spi_config *)spi->controller_data;

	if (!spicfg)

		spicfg = &davinci_spi_default_cfg;



	davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
@@ -834,8 +841,8 @@ static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t) 
		return ret;



	/* Put delay val if required */

	iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |

			(pdata->t2cdelay << SPI_T2CDELAY_SHIFT),

	iowrite32((spicfg->c2tdelay << SPI_C2TDELAY_SHIFT) |

			(spicfg->t2cdelay << SPI_T2CDELAY_SHIFT),

			davinci_spi->base + SPIDELAY);



	count = davinci_spi->count;	/* the number of elements */