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Commit 537d3b10 authored by Michał Winiarski's avatar Michał Winiarski Committed by Jani Nikula
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drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write 



We started to use PIPE_CONTROL to write render ring seqno in order to
combat seqno write vs interrupt generation problems. This was introduced
by commit 7c17d377 ("drm/i915: Use ordered seqno write interrupt
generation on gen8+ execlists").

On gen8+ size of PIPE_CONTROL with Post Sync Operation should be
6 dwords. When we're using older 5-dword variant it's possible to
observe inconsistent values written by PIPE_CONTROL with Post
Sync Operation from user batches, resulting in rendering corruptions.

v2: Fix BAT failures
v3: Comments on alignment and thrashing high dword of seqno (Chris)
v4: Updated commit msg (Mika)

Testcase: igt/gem_pipe_control_store_loop/*-qword-write
Issue: VIZ-7393
Cc: stable@vger.kernel.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: default avatarMichał Winiarski <michal.winiarski@intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Tested-by: default avatarAbdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460469115-26002-1-git-send-email-michal.winiarski@intel.com


(cherry picked from commit ce81a65c)
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 510650e8

drivers/gpu/drm/i915/intel_lrc.c

+8 −2
Original line number Original line Diff line number Diff line
@@ -1913,15 +1913,18 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request) 
	struct intel_ringbuffer *ringbuf = request->ringbuf;

	struct intel_ringbuffer *ringbuf = request->ringbuf;

	int ret;

	int ret;





	ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS);

	ret = intel_logical_ring_begin(request, 8 + WA_TAIL_DWORDS);

	if (ret)

	if (ret)

		return ret;

		return ret;





	/* We're using qword write, seqno should be aligned to 8 bytes. */

	BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);



	/* w/a for post sync ops following a GPGPU operation we

	/* w/a for post sync ops following a GPGPU operation we

	 * need a prior CS_STALL, which is emitted by the flush

	 * need a prior CS_STALL, which is emitted by the flush

	 * following the batch.

	 * following the batch.

	 */

	 */

	intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(5));

	intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));

	intel_logical_ring_emit(ringbuf,

	intel_logical_ring_emit(ringbuf,

				(PIPE_CONTROL_GLOBAL_GTT_IVB |

				(PIPE_CONTROL_GLOBAL_GTT_IVB |

				 PIPE_CONTROL_CS_STALL |

				 PIPE_CONTROL_CS_STALL |
@@ -1929,7 +1932,10 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request) 
	intel_logical_ring_emit(ringbuf, hws_seqno_address(request->ring));

	intel_logical_ring_emit(ringbuf, hws_seqno_address(request->ring));

	intel_logical_ring_emit(ringbuf, 0);

	intel_logical_ring_emit(ringbuf, 0);

	intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));

	intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));

	/* We're thrashing one dword of HWS. */

	intel_logical_ring_emit(ringbuf, 0);

	intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);

	intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);

	intel_logical_ring_emit(ringbuf, MI_NOOP);

	return intel_logical_ring_advance_and_submit(request);

	return intel_logical_ring_advance_and_submit(request);

}

}