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Commit 53286669 authored by Marc Zyngier's avatar Marc Zyngier Committed by Thomas Gleixner
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Documentation: Update IRQ-domain.txt to document irq_domain_mapping 



irq_domain_mapping is a rather useful tool to understand how IRqs
are mapped in irqdomains, and yet it is not documented anywhere.
Let's address this.

Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Link: http://lkml.kernel.org/r/20170512115538.10767-5-marc.zyngier@arm.com


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent a97b852b

Documentation/IRQ-domain.txt

+39 −2
Original line number Diff line number Diff line
@@ -231,5 +231,42 @@ needs to: 
4) No need to implement irq_domain_ops.map and irq_domain_ops.unmap,

   they are unused with hierarchy irq_domain.



Hierarchy irq_domain may also be used to support other architectures,

such as ARM, ARM64 etc.
 
Hierarchy irq_domain is in no way x86 specific, and is heavily used to

support other architectures, such as ARM, ARM64 etc.



=== Debugging ===



If you switch on CONFIG_IRQ_DOMAIN_DEBUG (which depends on

CONFIG_IRQ_DOMAIN and CONFIG_DEBUG_FS), you will find a new file in

your debugfs mount point, called irq_domain_mapping. This file

contains a live snapshot of all the IRQ domains in the system:



 name              mapped  linear-max  direct-max  devtree-node

 pl061                  8           8           0  /smb/gpio@e0080000

 pl061                  8           8           0  /smb/gpio@e1050000

 pMSI                   0           0           0  /interrupt-controller@e1101000/v2m@e0080000

 MSI                   37           0           0  /interrupt-controller@e1101000/v2m@e0080000

 GICv2m                37           0           0  /interrupt-controller@e1101000/v2m@e0080000

 GICv2                448         448           0  /interrupt-controller@e1101000



it also iterates over the interrupts to display their mapping in the

domains, and makes the domain stacking visible:





irq    hwirq    chip name        chip data           active  type            domain

    1  0x00019  GICv2            0xffff00000916bfd8     *    LINEAR          GICv2

    2  0x0001d  GICv2            0xffff00000916bfd8          LINEAR          GICv2

    3  0x0001e  GICv2            0xffff00000916bfd8     *    LINEAR          GICv2

    4  0x0001b  GICv2            0xffff00000916bfd8     *    LINEAR          GICv2

    5  0x0001a  GICv2            0xffff00000916bfd8          LINEAR          GICv2

[...]

   96  0x81808  MSI              0x          (null)           RADIX          MSI

   96+ 0x00063  GICv2m           0xffff8003ee116980           RADIX          GICv2m

   96+ 0x00063  GICv2            0xffff00000916bfd8          LINEAR          GICv2

   97  0x08800  MSI              0x          (null)     *     RADIX          MSI

   97+ 0x00064  GICv2m           0xffff8003ee116980     *     RADIX          GICv2m

   97+ 0x00064  GICv2            0xffff00000916bfd8     *    LINEAR          GICv2



Here, interrupts 1-5 are only using a single domain, while 96 and 97

are build out of a stack of three domain, each level performing a

particular function.