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Commit 51fe03c2 authored by Yujun Zhang's avatar Yujun Zhang Committed by Gerrit - the friendly Code Review server
Browse files

ARM: dts: msm: add dynamic clock switch support 

Enable dynamic clock switch feature for sw43404 amoled panel on
kona.
Correct inappropriate clock namings of dsi display for both kona
and lito.

Change-Id: Ie2c4bee1219f996a26cbd69ec04c9978e1ae2298
parent 5c879dbe

qcom/kona-sde-display.dtsi

+53 −5
Original line number Diff line number Diff line
@@ -150,10 +150,23 @@ 


		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,

			 <&mdss_dsi0_pll PCLK_SRC_0_CLK>,

			 <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>,

			 <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;

		clock-names = "src_byte_clk0", "src_pixel_clk0",

			      "src_byte_clk1", "src_pixel_clk1";

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>,

			 <&mdss_dsi1_pll PCLK_SRC_1_CLK>,

			 <&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>,

			 <&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>;



		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

				"src_byte_clk0", "src_pixel_clk0",

				"shadow_byte_clk0", "shadow_pixel_clk0",

				"mux_byte_clk1", "mux_pixel_clk1",

				"src_byte_clk1", "src_pixel_clk1",

				"shadow_byte_clk1", "shadow_pixel_clk1";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
@@ -181,8 +194,8 @@ 
			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;

		clock-names = "src_byte_clk0", "src_pixel_clk0",

			      "src_byte_clk1", "src_pixel_clk1";

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

			      "mux_byte_clk1", "mux_pixel_clk1";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
@@ -230,6 +243,14 @@ 
	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";

	qcom,mdss-dsi-panel-status-value = <0x9c>;

	qcom,mdss-dsi-panel-status-read-length = <1>;



	qcom,dsi-dyn-clk-enable;

	qcom,dsi-dyn-clk-list = <606979440 604450359 601921278>;



	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",

				"src_byte_clk0", "src_pixel_clk0",

				"shadow_byte_clk0", "shadow_pixel_clk0";



	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
@@ -254,6 +275,15 @@ 
	qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp";

	qcom,mdss-dsi-min-refresh-rate = <55>;

	qcom,mdss-dsi-max-refresh-rate = <60>;



	qcom,dsi-dyn-clk-enable;

	qcom,dsi-dyn-clk-list =

		<534712320 532484352 530256384>;



	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",

				"src_byte_clk0", "src_pixel_clk0",

				"shadow_byte_clk0", "shadow_pixel_clk0";



	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
@@ -272,6 +302,7 @@ 
	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";

	qcom,mdss-dsi-panel-status-value = <0x9c>;

	qcom,mdss-dsi-panel-status-read-length = <1>;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04
@@ -286,6 +317,7 @@ 


&dsi_sharp_4k_dsc_cmd {

	qcom,ulps-enabled;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
@@ -297,6 +329,7 @@ 
};



&dsi_sharp_4k_dsc_video {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
@@ -308,6 +341,7 @@ 
};



&dsi_sharp_qsync_wqhd_cmd {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 1d 1c 03
@@ -319,6 +353,7 @@ 
};



&dsi_sharp_qsync_wqhd_video {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1f 05
@@ -331,6 +366,7 @@ 


&dsi_sharp_1080_cmd {

	qcom,ulps-enabled;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1E 08 08 24 22 08
@@ -344,6 +380,7 @@ 


&dsi_dual_nt35597_truly_cmd {

	qcom,ulps-enabled;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -356,6 +393,7 @@ 
};



&dsi_dual_nt35597_truly_video {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-min-refresh-rate = <53>;

	qcom,mdss-dsi-max-refresh-rate = <60>;

	qcom,mdss-dsi-pan-enable-dynamic-fps;
@@ -373,6 +411,7 @@ 


&dsi_nt35695b_truly_fhd_cmd {

	qcom,ulps-enabled;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
@@ -384,6 +423,7 @@ 
};



&dsi_nt35695b_truly_fhd_video {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
@@ -396,6 +436,7 @@ 


&dsi_sim_cmd {

	qcom,ulps-enabled;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -446,6 +487,7 @@ 
};



&dsi_sim_vid {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -459,6 +501,7 @@ 


&dsi_sim_dsc_375_cmd {

	qcom,ulps-enabled;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 { /* 1080p */

			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -480,6 +523,7 @@ 


&dsi_sim_dsc_10b_cmd {

	qcom,ulps-enabled;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 { /* QHD 60fps */

			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -508,6 +552,7 @@ 


&dsi_dual_sim_cmd {

	qcom,ulps-enabled;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
@@ -534,6 +579,7 @@ 
};



&dsi_dual_sim_vid {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -547,6 +593,7 @@ 


&dsi_dual_sim_dsc_375_cmd {

	qcom,ulps-enabled;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 { /* qhd */

			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -573,6 +620,7 @@ 


&dsi_sim_sec_hd_cmd {

	qcom,ulps-enabled;

	qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22

qcom/kona-sde-pll.dtsi

+9 −4
Original line number Diff line number Diff line
@@ -6,11 +6,14 @@ 
		#clock-cells = <1>;

		reg = <0xae94900 0x260>,

		      <0xae94400 0x800>,

		      <0xaf03000 0x8>;

		reg-names = "pll_base", "phy_base", "gdsc_base";

		      <0xaf03000 0x8>,

		      <0xae94200 0x100>;

		reg-names = "pll_base", "phy_base", "gdsc_base",

				"dynamic_pll_base";

		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;

		clock-names = "iface_clk";

		clock-rate = <0>;

		memory-region = <&dfps_data_memory>;

		gdsc-supply = <&mdss_core_gdsc>;

		qcom,dsi-pll-ssc-en;

		qcom,dsi-pll-ssc-mode = "down-spread";
@@ -35,8 +38,10 @@ 
		#clock-cells = <1>;

		reg = <0xae96900 0x260>,

		      <0xae96400 0x800>,

		      <0xaf03000 0x8>;

		reg-names = "pll_base", "phy_base", "gdsc_base";

		      <0xaf03000 0x8>,

		      <0xae96200 0x100>;

		reg-names = "pll_base", "phy_base", "gdsc_base",

				"dynamic_pll_base";

		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;

		clock-names = "iface_clk";

		clock-rate = <0>;

qcom/kona-sde.dtsi

+6 −4
Original line number Diff line number Diff line
@@ -623,8 +623,9 @@ 
		compatible = "qcom,dsi-phy-v4.1";

		label = "dsi-phy-0";

		cell-index = <0>;

		reg = <0xae94400 0x760>;

		reg-names = "dsi_phy";

		reg = <0xae94400 0x7c0>,

			<0xae94200 0x100>;

		reg-names = "dsi_phy", "dyn_refresh_base";

		vdda-0p9-supply = <&pm8150_l5>;

		qcom,platform-strength-ctrl = [55 03

						55 03
@@ -655,8 +656,9 @@ 
		compatible = "qcom,dsi-phy-v4.1";

		label = "dsi-phy-1";

		cell-index = <1>;

		reg = <0xae96400 0x760>;

		reg-names = "dsi_phy";

		reg = <0xae96400 0x7c0>,

			<0xae96200 0x100>;

		reg-names = "dsi_phy", "dyn_refresh_base";

		vdda-0p9-supply = <&pm8150_l5>;

		qcom,platform-strength-ctrl = [55 03

						55 03

qcom/kona.dtsi

+6 −1
Original line number Diff line number Diff line
@@ -607,7 +607,7 @@ 
		};



		cont_splash_memory: cont_splash_region@9c000000 {

			reg = <0x0 0x9c000000 0x0 0x02400000>;

			reg = <0x0 0x9c000000 0x0 0x02300000>;

			label = "cont_splash_region";

		};
@@ -616,6 +616,11 @@ 
			label = "disp_rdump_region";

		};



		dfps_data_memory: dfps_data_region@9e300000 {

			reg = <0x0 0x9e300000 0x0 0x0100000>;

			label = "dfps_data_region";

		};



		dump_mem: mem_dump_region {

			compatible = "shared-dma-pool";

			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;

qcom/lito-sde-display.dtsi

+35 −5
Original line number Diff line number Diff line
@@ -109,10 +109,22 @@ 


		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,

			 <&mdss_dsi0_pll PCLK_SRC_0_CLK>,

			 <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>,

			 <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;

		clock-names = "src_byte_clk0", "src_pixel_clk0",

			      "src_byte_clk1", "src_pixel_clk1";

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>,

			 <&mdss_dsi1_pll PCLK_SRC_1_CLK>,

			 <&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>,

			 <&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>;

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

				"src_byte_clk0", "src_pixel_clk0",

				"shadow_byte_clk0", "shadow_pixel_clk0",

				"mux_byte_clk1", "mux_pixel_clk1",

				"src_byte_clk1", "src_pixel_clk1",

				"shadow_byte_clk1", "shadow_pixel_clk1";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_te_active &disp_pins_default>;
@@ -139,8 +151,8 @@ 
			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;

		clock-names = "src_byte_clk0", "src_pixel_clk0",

			      "src_byte_clk1", "src_pixel_clk1";

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

			      "mux_byte_clk1", "mux_pixel_clk1";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_te1_active>;
@@ -187,6 +199,9 @@ 
	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";

	qcom,mdss-dsi-panel-status-value = <0x9c>;

	qcom,mdss-dsi-panel-status-read-length = <1>;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",

				"src_byte_clk0", "src_pixel_clk0",

				"shadow_byte_clk0", "shadow_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
@@ -211,6 +226,9 @@ 
	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";

	qcom,mdss-dsi-panel-status-value = <0x9c>;

	qcom,mdss-dsi-panel-status-read-length = <1>;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",

				"src_byte_clk0", "src_pixel_clk0",

				"shadow_byte_clk0", "shadow_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
@@ -229,6 +247,7 @@ 
	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";

	qcom,mdss-dsi-panel-status-value = <0x9c>;

	qcom,mdss-dsi-panel-status-read-length = <1>;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04
@@ -243,6 +262,7 @@ 


&dsi_sim_cmd {

	qcom,ulps-enabled;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -293,6 +313,7 @@ 
};



&dsi_sim_vid {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -306,6 +327,7 @@ 


&dsi_sim_dsc_375_cmd {

	qcom,ulps-enabled;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 { /* 1080p */

			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -327,6 +349,7 @@ 


&dsi_dual_sim_cmd {

	qcom,ulps-enabled;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
@@ -353,6 +376,7 @@ 
};



&dsi_dual_sim_vid {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -366,6 +390,7 @@ 


&dsi_dual_sim_dsc_375_cmd {

	qcom,ulps-enabled;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 { /* qhd */

			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -392,6 +417,7 @@ 


&dsi_sim_sec_hd_cmd {

	qcom,ulps-enabled;

	qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
@@ -405,6 +431,7 @@ 
};



&dsi_dual_sharp_wqhd_video {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1b 07 06 22 21
@@ -416,6 +443,7 @@ 
};



&dsi_dual_sharp_wqhd_cmd {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1b 07 06 22 21
@@ -428,6 +456,7 @@ 


&dsi_sharp_4k_dsc_cmd {

	qcom,ulps-enabled;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
@@ -439,6 +468,7 @@ 
};



&dsi_sharp_4k_dsc_video {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08