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Commit 51fbba42 authored by Maxime Ripard's avatar Maxime Ripard
Browse files

ARM: sun5i: a13: Move to the common sun5i DTSI 



Now that we have a common DTSI for the sun5i family, move the A13 to use it.

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent fbfa7367

arch/arm/boot/dts/sun5i-a13.dtsi

+37 −515
Original line number Diff line number Diff line
@@ -49,10 +49,10 @@ 


#include "skeleton.dtsi"



#include <dt-bindings/thermal/thermal.h>

#include "sun5i.dtsi"



#include <dt-bindings/dma/sun4i-a10.h>

#include <dt-bindings/pinctrl/sun4i-a10.h>

#include <dt-bindings/thermal/thermal.h>



/ {

	interrupt-parent = <&intc>;
@@ -71,31 +71,6 @@ 
		};

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a8";

			reg = <0x0>;

			clocks = <&cpu>;

			clock-latency = <244144>; /* 8 32k periods */

			operating-points = <

				/* kHz    uV */

				1008000 1400000

				912000  1350000

				864000  1300000

				624000  1200000

				576000  1200000

				432000  1200000

				>;

			#cooling-cells = <2>;

			cooling-min-level = <0>;

			cooling-max-level = <5>;

		};

	};



	thermal-zones {

		cpu_thermal {

			/* milliseconds */
@@ -128,107 +103,7 @@ 
		};

	};



	memory {

		reg = <0x40000000 0x20000000>;

	};



	clocks {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		/*

		 * This is a dummy clock, to be used as placeholder on

		 * other mux clocks when a specific parent clock is not

		 * yet implemented. It should be dropped when the driver

		 * is complete.

		 */

		dummy: dummy {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <0>;

		};



		osc24M: clk@01c20050 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-osc-clk";

			reg = <0x01c20050 0x4>;

			clock-frequency = <24000000>;

			clock-output-names = "osc24M";

		};



		osc32k: clk@0 {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <32768>;

			clock-output-names = "osc32k";

		};



		pll1: clk@01c20000 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-pll1-clk";

			reg = <0x01c20000 0x4>;

			clocks = <&osc24M>;

			clock-output-names = "pll1";

		};



		pll4: clk@01c20018 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-pll1-clk";

			reg = <0x01c20018 0x4>;

			clocks = <&osc24M>;

			clock-output-names = "pll4";

		};



		pll5: clk@01c20020 {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-pll5-clk";

			reg = <0x01c20020 0x4>;

			clocks = <&osc24M>;

			clock-output-names = "pll5_ddr", "pll5_other";

		};



		pll6: clk@01c20028 {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-pll6-clk";

			reg = <0x01c20028 0x4>;

			clocks = <&osc24M>;

			clock-output-names = "pll6_sata", "pll6_other", "pll6";

		};



		/* dummy is 200M */

		cpu: cpu@01c20054 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-cpu-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;

			clock-output-names = "cpu";

		};



		axi: axi@01c20054 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-axi-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&cpu>;

			clock-output-names = "axi";

		};



		axi_gates: clk@01c2005c {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-axi-gates-clk";

			reg = <0x01c2005c 0x4>;

			clocks = <&axi>;

			clock-output-names = "axi_dram";

		};



		ahb: ahb@01c20054 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-ahb-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&axi>;

			clock-output-names = "ahb";

		};



		ahb_gates: clk@01c20060 {

			#clock-cells = <1>;

			compatible = "allwinner,sun5i-a13-ahb-gates-clk";
@@ -242,14 +117,6 @@ 
				"ahb_de_fe", "ahb_iep", "ahb_mali400";

		};



		apb0: apb0@01c20054 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-apb0-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&ahb>;

			clock-output-names = "apb0";

		};



		apb0_gates: clk@01c20068 {

			#clock-cells = <1>;

			compatible = "allwinner,sun5i-a13-apb0-gates-clk";
@@ -258,14 +125,6 @@ 
			clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";

		};



		apb1: clk@01c20058 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-apb1-clk";

			reg = <0x01c20058 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;

			clock-output-names = "apb1";

		};



		apb1_gates: clk@01c2006c {

			#clock-cells = <1>;

			compatible = "allwinner,sun5i-a13-apb1-gates-clk";
@@ -274,254 +133,35 @@ 
			clock-output-names = "apb1_i2c0", "apb1_i2c1",

				"apb1_i2c2", "apb1_uart1", "apb1_uart3";

		};



		nand_clk: clk@01c20080 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c20080 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "nand";

		};



		ms_clk: clk@01c20084 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c20084 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "ms";

		};



		mmc0_clk: clk@01c20088 {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20088 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc0",

					     "mmc0_output",

					     "mmc0_sample";

		};



		mmc1_clk: clk@01c2008c {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c2008c 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc1",

					     "mmc1_output",

					     "mmc1_sample";

		};



		mmc2_clk: clk@01c20090 {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20090 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc2",

					     "mmc2_output",

					     "mmc2_sample";

		};



		ts_clk: clk@01c20098 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c20098 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "ts";

		};



		ss_clk: clk@01c2009c {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c2009c 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "ss";

		};



		spi0_clk: clk@01c200a0 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c200a0 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "spi0";

		};



		spi1_clk: clk@01c200a4 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c200a4 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "spi1";

		};



		spi2_clk: clk@01c200a8 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c200a8 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "spi2";

		};



		ir0_clk: clk@01c200b0 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c200b0 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "ir0";

	};



		usb_clk: clk@01c200cc {

			#clock-cells = <1>;

		        #reset-cells = <1>;

			compatible = "allwinner,sun5i-a13-usb-clk";

			reg = <0x01c200cc 0x4>;

			clocks = <&pll6 1>;

			clock-output-names = "usb_ohci0", "usb_phy";

};



		mbus_clk: clk@01c2015c {

			#clock-cells = <0>;

			compatible = "allwinner,sun5i-a13-mbus-clk";

			reg = <0x01c2015c 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mbus";

		};

	};



	soc@01c00000 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		dma: dma-controller@01c02000 {

			compatible = "allwinner,sun4i-a10-dma";

			reg = <0x01c02000 0x1000>;

			interrupts = <27>;

			clocks = <&ahb_gates 6>;

			#dma-cells = <2>;

		};



		spi0: spi@01c05000 {

			compatible = "allwinner,sun4i-a10-spi";

			reg = <0x01c05000 0x1000>;

			interrupts = <10>;

			clocks = <&ahb_gates 20>, <&spi0_clk>;

			clock-names = "ahb", "mod";

			dmas = <&dma SUN4I_DMA_DEDICATED 27>,

			       <&dma SUN4I_DMA_DEDICATED 26>;

			dma-names = "rx", "tx";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		spi1: spi@01c06000 {

			compatible = "allwinner,sun4i-a10-spi";

			reg = <0x01c06000 0x1000>;

			interrupts = <11>;

			clocks = <&ahb_gates 21>, <&spi1_clk>;

			clock-names = "ahb", "mod";

			dmas = <&dma SUN4I_DMA_DEDICATED 9>,

			       <&dma SUN4I_DMA_DEDICATED 8>;

			dma-names = "rx", "tx";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		mmc0: mmc@01c0f000 {

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c0f000 0x1000>;

			clocks = <&ahb_gates 8>,

				 <&mmc0_clk 0>,

				 <&mmc0_clk 1>,

				 <&mmc0_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <32>;

			status = "disabled";

		};



		mmc2: mmc@01c11000 {

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c11000 0x1000>;

			clocks = <&ahb_gates 10>,

				 <&mmc2_clk 0>,

				 <&mmc2_clk 1>,

				 <&mmc2_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <34>;

			status = "disabled";

		};



		usbphy: phy@01c13400 {

			#phy-cells = <1>;

			compatible = "allwinner,sun5i-a13-usb-phy";

			reg = <0x01c13400 0x10 0x01c14800 0x4>;

			reg-names = "phy_ctrl", "pmu1";

			clocks = <&usb_clk 8>;

			clock-names = "usb_phy";

			resets = <&usb_clk 0>, <&usb_clk 1>;

			reset-names = "usb0_reset", "usb1_reset";

			status = "disabled";

&cpu0 {

	clock-latency = <244144>; /* 8 32k periods */

	operating-points = <

		/* kHz    uV */

		1008000 1400000

		912000  1350000

		864000  1300000

		624000  1200000

		576000  1200000

		432000  1200000

		>;

	#cooling-cells = <2>;

	cooling-min-level = <0>;

	cooling-max-level = <5>;

};



		ehci0: usb@01c14000 {

&ehci0 {

	compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";

			reg = <0x01c14000 0x100>;

			interrupts = <39>;

			clocks = <&ahb_gates 1>;

			phys = <&usbphy 1>;

			phy-names = "usb";

			status = "disabled";

};



		ohci0: usb@01c14400 {

&ohci0 {

	compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";

			reg = <0x01c14400 0x100>;

			interrupts = <40>;

			clocks = <&usb_clk 6>, <&ahb_gates 2>;

			phys = <&usbphy 1>;

			phy-names = "usb";

			status = "disabled";

		};



		spi2: spi@01c17000 {

			compatible = "allwinner,sun4i-a10-spi";

			reg = <0x01c17000 0x1000>;

			interrupts = <12>;

			clocks = <&ahb_gates 22>, <&spi2_clk>;

			clock-names = "ahb", "mod";

			dmas = <&dma SUN4I_DMA_DEDICATED 29>,

			       <&dma SUN4I_DMA_DEDICATED 28>;

			dma-names = "rx", "tx";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

};



		intc: interrupt-controller@01c20400 {

			compatible = "allwinner,sun4i-a10-ic";

			reg = <0x01c20400 0x400>;

			interrupt-controller;

			#interrupt-cells = <1>;

		};



		pio: pinctrl@01c20800 {

&pio {

	compatible = "allwinner,sun5i-a13-pinctrl";

			reg = <0x01c20800 0x400>;

			interrupts = <28>;

			clocks = <&apb0_gates 5>;

			gpio-controller;

			interrupt-controller;

			#interrupt-cells = <2>;

			#size-cells = <0>;

			#gpio-cells = <3>;



	uart1_pins_a: uart1@0 {

		allwinner,pins = "PE10", "PE11";
@@ -536,122 +176,4 @@ 
		allwinner,drive = <SUN4I_PINCTRL_10_MA>;

		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

	};



			i2c0_pins_a: i2c0@0 {

				allwinner,pins = "PB0", "PB1";

				allwinner,function = "i2c0";

				allwinner,drive = <SUN4I_PINCTRL_10_MA>;

				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

			};



			i2c1_pins_a: i2c1@0 {

				allwinner,pins = "PB15", "PB16";

				allwinner,function = "i2c1";

				allwinner,drive = <SUN4I_PINCTRL_10_MA>;

				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

			};



			i2c2_pins_a: i2c2@0 {

				allwinner,pins = "PB17", "PB18";

				allwinner,function = "i2c2";

				allwinner,drive = <SUN4I_PINCTRL_10_MA>;

				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

			};



			mmc0_pins_a: mmc0@0 {

				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";

				allwinner,function = "mmc0";

				allwinner,drive = <SUN4I_PINCTRL_30_MA>;

				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

			};

		};



		timer@01c20c00 {

			compatible = "allwinner,sun4i-a10-timer";

			reg = <0x01c20c00 0x90>;

			interrupts = <22>;

			clocks = <&osc24M>;

		};



		wdt: watchdog@01c20c90 {

			compatible = "allwinner,sun4i-a10-wdt";

			reg = <0x01c20c90 0x10>;

		};



		lradc: lradc@01c22800 {

			compatible = "allwinner,sun4i-a10-lradc-keys";

			reg = <0x01c22800 0x100>;

			interrupts = <31>;

			status = "disabled";

		};



		sid: eeprom@01c23800 {

			compatible = "allwinner,sun4i-a10-sid";

			reg = <0x01c23800 0x10>;

		};



		rtp: rtp@01c25000 {

			compatible = "allwinner,sun4i-a10-ts";

			reg = <0x01c25000 0x100>;

			interrupts = <29>;

			#thermal-sensor-cells = <0>;

		};



		uart1: serial@01c28400 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28400 0x400>;

			interrupts = <2>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&apb1_gates 17>;

			status = "disabled";

		};



		uart3: serial@01c28c00 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28c00 0x400>;

			interrupts = <4>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&apb1_gates 19>;

			status = "disabled";

		};



		i2c0: i2c@01c2ac00 {

			compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";

			reg = <0x01c2ac00 0x400>;

			interrupts = <7>;

			clocks = <&apb1_gates 0>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		i2c1: i2c@01c2b000 {

			compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";

			reg = <0x01c2b000 0x400>;

			interrupts = <8>;

			clocks = <&apb1_gates 1>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		i2c2: i2c@01c2b400 {

			compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";

			reg = <0x01c2b400 0x400>;

			interrupts = <9>;

			clocks = <&apb1_gates 2>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		timer@01c60000 {

			compatible = "allwinner,sun5i-a13-hstimer";

			reg = <0x01c60000 0x1000>;

			interrupts = <82>, <83>;

			clocks = <&ahb_gates 28>;

		};

	};

};

arch/arm/boot/dts/sun5i.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -439,6 +439,34 @@ 
			#interrupt-cells = <2>;

			#size-cells = <0>;

			#gpio-cells = <3>;



			i2c0_pins_a: i2c0@0 {

				allwinner,pins = "PB0", "PB1";

				allwinner,function = "i2c0";

				allwinner,drive = <SUN4I_PINCTRL_10_MA>;

				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

			};



			i2c1_pins_a: i2c1@0 {

				allwinner,pins = "PB15", "PB16";

				allwinner,function = "i2c1";

				allwinner,drive = <SUN4I_PINCTRL_10_MA>;

				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

			};



			i2c2_pins_a: i2c2@0 {

				allwinner,pins = "PB17", "PB18";

				allwinner,function = "i2c2";

				allwinner,drive = <SUN4I_PINCTRL_10_MA>;

				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

			};



			mmc0_pins_a: mmc0@0 {

				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";

				allwinner,function = "mmc0";

				allwinner,drive = <SUN4I_PINCTRL_30_MA>;

				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

			};

		};



		timer@01c20c00 {