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Commit 51cea1f4 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Fix pipe enabled mask for pipe C in WM calculations 



Fix the incorrect enabled pipes mask for pipe C in the WM calculations.

Additionally, in an effort to make the code easier to understand,
populate the mask with 1 << PIPE_[ABC] instead of raw numbers.

v2: Use 1 << PIPE_[ABC] (ickle/danvet)
v3: Pass PIPE_[ABC] to g4x_compute_wm0() (ickle)

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3a359f0b

drivers/gpu/drm/i915/intel_pm.c

+22 −22
Original line number Diff line number Diff line
@@ -1301,17 +1301,17 @@ static void valleyview_update_wm(struct drm_device *dev) 


	vlv_update_drain_latency(dev);



	if (g4x_compute_wm0(dev, 0,

	if (g4x_compute_wm0(dev, PIPE_A,

			    &valleyview_wm_info, latency_ns,

			    &valleyview_cursor_wm_info, latency_ns,

			    &planea_wm, &cursora_wm))

		enabled |= 1;

		enabled |= 1 << PIPE_A;



	if (g4x_compute_wm0(dev, 1,

	if (g4x_compute_wm0(dev, PIPE_B,

			    &valleyview_wm_info, latency_ns,

			    &valleyview_cursor_wm_info, latency_ns,

			    &planeb_wm, &cursorb_wm))

		enabled |= 2;

		enabled |= 1 << PIPE_B;



	if (single_plane_enabled(enabled) &&

	    g4x_compute_srwm(dev, ffs(enabled) - 1,
@@ -1357,17 +1357,17 @@ static void g4x_update_wm(struct drm_device *dev) 
	int plane_sr, cursor_sr;

	unsigned int enabled = 0;



	if (g4x_compute_wm0(dev, 0,

	if (g4x_compute_wm0(dev, PIPE_A,

			    &g4x_wm_info, latency_ns,

			    &g4x_cursor_wm_info, latency_ns,

			    &planea_wm, &cursora_wm))

		enabled |= 1;

		enabled |= 1 << PIPE_A;



	if (g4x_compute_wm0(dev, 1,

	if (g4x_compute_wm0(dev, PIPE_B,

			    &g4x_wm_info, latency_ns,

			    &g4x_cursor_wm_info, latency_ns,

			    &planeb_wm, &cursorb_wm))

		enabled |= 2;

		enabled |= 1 << PIPE_B;



	if (single_plane_enabled(enabled) &&

	    g4x_compute_srwm(dev, ffs(enabled) - 1,
@@ -1716,7 +1716,7 @@ static void ironlake_update_wm(struct drm_device *dev) 
	unsigned int enabled;



	enabled = 0;

	if (g4x_compute_wm0(dev, 0,

	if (g4x_compute_wm0(dev, PIPE_A,

			    &ironlake_display_wm_info,

			    ILK_LP0_PLANE_LATENCY,

			    &ironlake_cursor_wm_info,
@@ -1727,10 +1727,10 @@ static void ironlake_update_wm(struct drm_device *dev) 
		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"

			      " plane %d, " "cursor: %d\n",

			      plane_wm, cursor_wm);

		enabled |= 1;

		enabled |= 1 << PIPE_A;

	}



	if (g4x_compute_wm0(dev, 1,

	if (g4x_compute_wm0(dev, PIPE_B,

			    &ironlake_display_wm_info,

			    ILK_LP0_PLANE_LATENCY,

			    &ironlake_cursor_wm_info,
@@ -1741,7 +1741,7 @@ static void ironlake_update_wm(struct drm_device *dev) 
		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"

			      " plane %d, cursor: %d\n",

			      plane_wm, cursor_wm);

		enabled |= 2;

		enabled |= 1 << PIPE_B;

	}



	/*
@@ -1801,7 +1801,7 @@ static void sandybridge_update_wm(struct drm_device *dev) 
	unsigned int enabled;



	enabled = 0;

	if (g4x_compute_wm0(dev, 0,

	if (g4x_compute_wm0(dev, PIPE_A,

			    &sandybridge_display_wm_info, latency,

			    &sandybridge_cursor_wm_info, latency,

			    &plane_wm, &cursor_wm)) {
@@ -1812,10 +1812,10 @@ static void sandybridge_update_wm(struct drm_device *dev) 
		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"

			      " plane %d, " "cursor: %d\n",

			      plane_wm, cursor_wm);

		enabled |= 1;

		enabled |= 1 << PIPE_A;

	}



	if (g4x_compute_wm0(dev, 1,

	if (g4x_compute_wm0(dev, PIPE_B,

			    &sandybridge_display_wm_info, latency,

			    &sandybridge_cursor_wm_info, latency,

			    &plane_wm, &cursor_wm)) {
@@ -1826,7 +1826,7 @@ static void sandybridge_update_wm(struct drm_device *dev) 
		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"

			      " plane %d, cursor: %d\n",

			      plane_wm, cursor_wm);

		enabled |= 2;

		enabled |= 1 << PIPE_B;

	}



	/*
@@ -1904,7 +1904,7 @@ static void ivybridge_update_wm(struct drm_device *dev) 
	unsigned int enabled;



	enabled = 0;

	if (g4x_compute_wm0(dev, 0,

	if (g4x_compute_wm0(dev, PIPE_A,

			    &sandybridge_display_wm_info, latency,

			    &sandybridge_cursor_wm_info, latency,

			    &plane_wm, &cursor_wm)) {
@@ -1915,10 +1915,10 @@ static void ivybridge_update_wm(struct drm_device *dev) 
		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"

			      " plane %d, " "cursor: %d\n",

			      plane_wm, cursor_wm);

		enabled |= 1;

		enabled |= 1 << PIPE_A;

	}



	if (g4x_compute_wm0(dev, 1,

	if (g4x_compute_wm0(dev, PIPE_B,

			    &sandybridge_display_wm_info, latency,

			    &sandybridge_cursor_wm_info, latency,

			    &plane_wm, &cursor_wm)) {
@@ -1929,10 +1929,10 @@ static void ivybridge_update_wm(struct drm_device *dev) 
		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"

			      " plane %d, cursor: %d\n",

			      plane_wm, cursor_wm);

		enabled |= 2;

		enabled |= 1 << PIPE_B;

	}



	if (g4x_compute_wm0(dev, 2,

	if (g4x_compute_wm0(dev, PIPE_C,

			    &sandybridge_display_wm_info, latency,

			    &sandybridge_cursor_wm_info, latency,

			    &plane_wm, &cursor_wm)) {
@@ -1943,7 +1943,7 @@ static void ivybridge_update_wm(struct drm_device *dev) 
		DRM_DEBUG_KMS("FIFO watermarks For pipe C -"

			      " plane %d, cursor: %d\n",

			      plane_wm, cursor_wm);

		enabled |= 3;

		enabled |= 1 << PIPE_C;

	}



	/*