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Commit 51bce5bc authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2015-12-04-1' of git://anongit.freedesktop.org/drm-intel into drm-next 

This is the "fix igt basic test set issues" edition.
- more PSR fixes from Rodrigo, getting closer
- tons of fifo underrun fixes from Ville
- runtime pm fixes from Imre, Daniel Stone
- fix SDE interrupt handling properly (Jani Nikula)
- hsw/bdw fdi modeset sequence fixes (Ville)
- "don't register bad VGA connectors and fall over" fixes (Ville)
- more fbc fixes from Paulo
- and a grand total of exactly one feature item: Implement dma-buf/fence based
  cross-driver sync in the i915 pageflip path (Alex Goins)

* tag 'drm-intel-next-2015-12-04-1' of git://anongit.freedesktop.org/drm-intel: (70 commits)
  drm/i915: Update DRIVER_DATE to 20151204
  drm/i915/skl: Add SKL GT4 PCI IDs
  Revert "drm/i915: Extend LRC pinning to cover GPU context writeback"
  drm/i915: Correct the Ref clock value for BXT
  drm/i915: Restore skl_gt3 device info
  drm/i915: Fix RPS pointer passed from wait_ioctl to i915_wait_request
  Revert "drm/i915: Remove superfluous NULL check"
  drm/i915: Clean up device info structure definitions
  drm/i915: Remove superfluous NULL check
  drm/i915: Handle cdclk limits on broadwell.
  i915: wait for fence in prepare_plane_fb
  i915: wait for fence in mmio_flip_work_func
  drm/i915: Extend LRC pinning to cover GPU context writeback
  drm/i915/guc: Clean up locks in GuC
  drm/i915: only recompress FBC after flushing a drawing operation
  drm/i915: get rid of FBC {,de}activation messages
  drm/i915: kill fbc.uncompressed_size
  drm/i915: use a single intel_fbc_work struct
  drm/i915: check for FBC planes in the same place as the pipes
  drm/i915: alloc/free the FBC CFB during enable/disable
  ...
parents eb227c55 03a97d82

drivers/gpu/drm/i915/i915_debugfs.c

+29 −95
Original line number Diff line number Diff line
@@ -1639,7 +1639,7 @@ static int i915_fbc_status(struct seq_file *m, void *unused) 
	intel_runtime_pm_get(dev_priv);

	mutex_lock(&dev_priv->fbc.lock);



	if (intel_fbc_enabled(dev_priv))

	if (intel_fbc_is_active(dev_priv))

		seq_puts(m, "FBC enabled\n");

	else

		seq_printf(m, "FBC disabled: %s\n",
@@ -1869,33 +1869,29 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data) 
{

	struct drm_info_node *node = m->private;

	struct drm_device *dev = node->minor->dev;

	struct intel_fbdev *ifbdev = NULL;

	struct intel_framebuffer *fb;

	struct intel_framebuffer *fbdev_fb = NULL;

	struct drm_framebuffer *drm_fb;



#ifdef CONFIG_DRM_FBDEV_EMULATION

	struct drm_i915_private *dev_priv = dev->dev_private;



	ifbdev = dev_priv->fbdev;

	if (ifbdev) {

		fb = to_intel_framebuffer(ifbdev->helper.fb);

       if (to_i915(dev)->fbdev) {

               fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);



               seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",

			   fb->base.width,

			   fb->base.height,

			   fb->base.depth,

			   fb->base.bits_per_pixel,

			   fb->base.modifier[0],

			   atomic_read(&fb->base.refcount.refcount));

		describe_obj(m, fb->obj);

                         fbdev_fb->base.width,

                         fbdev_fb->base.height,

                         fbdev_fb->base.depth,

                         fbdev_fb->base.bits_per_pixel,

                         fbdev_fb->base.modifier[0],

                         atomic_read(&fbdev_fb->base.refcount.refcount));

               describe_obj(m, fbdev_fb->obj);

               seq_putc(m, '\n');

       }

#endif



	mutex_lock(&dev->mode_config.fb_lock);

	drm_for_each_fb(drm_fb, dev) {

		fb = to_intel_framebuffer(drm_fb);

		if (ifbdev && &fb->base == ifbdev->helper.fb)

		struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);

		if (fb == fbdev_fb)

			continue;



		seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
@@ -2473,15 +2469,15 @@ static int i915_guc_info(struct seq_file *m, void *data) 
	if (!HAS_GUC_SCHED(dev_priv->dev))

		return 0;



	if (mutex_lock_interruptible(&dev->struct_mutex))

		return 0;



	/* Take a local copy of the GuC data, so we can dump it at leisure */

	spin_lock(&dev_priv->guc.host2guc_lock);

	guc = dev_priv->guc;

	if (guc.execbuf_client) {

		spin_lock(&guc.execbuf_client->wq_lock);

	if (guc.execbuf_client)

		client = *guc.execbuf_client;

		spin_unlock(&guc.execbuf_client->wq_lock);

	}

	spin_unlock(&dev_priv->guc.host2guc_lock);



	mutex_unlock(&dev->struct_mutex);



	seq_printf(m, "GuC total action count: %llu\n", guc.action_count);

	seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
@@ -2582,8 +2578,11 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) 
		}

	seq_puts(m, "\n");



	/* CHV PSR has no kind of performance counter */

	if (HAS_DDI(dev)) {

	/*

	 * VLV/CHV PSR has no kind of performance counter

	 * SKL+ Perf counter is reset to 0 everytime DC state is entered

	 */

	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {

		psrperf = I915_READ(EDP_PSR_PERF_CNT) &

			EDP_PSR_PERF_CNT_MASK;
@@ -2685,71 +2684,6 @@ static int i915_runtime_pm_status(struct seq_file *m, void *unused) 
	return 0;

}



static const char *power_domain_str(enum intel_display_power_domain domain)

{

	switch (domain) {

	case POWER_DOMAIN_PIPE_A:

		return "PIPE_A";

	case POWER_DOMAIN_PIPE_B:

		return "PIPE_B";

	case POWER_DOMAIN_PIPE_C:

		return "PIPE_C";

	case POWER_DOMAIN_PIPE_A_PANEL_FITTER:

		return "PIPE_A_PANEL_FITTER";

	case POWER_DOMAIN_PIPE_B_PANEL_FITTER:

		return "PIPE_B_PANEL_FITTER";

	case POWER_DOMAIN_PIPE_C_PANEL_FITTER:

		return "PIPE_C_PANEL_FITTER";

	case POWER_DOMAIN_TRANSCODER_A:

		return "TRANSCODER_A";

	case POWER_DOMAIN_TRANSCODER_B:

		return "TRANSCODER_B";

	case POWER_DOMAIN_TRANSCODER_C:

		return "TRANSCODER_C";

	case POWER_DOMAIN_TRANSCODER_EDP:

		return "TRANSCODER_EDP";

	case POWER_DOMAIN_PORT_DDI_A_LANES:

		return "PORT_DDI_A_LANES";

	case POWER_DOMAIN_PORT_DDI_B_LANES:

		return "PORT_DDI_B_LANES";

	case POWER_DOMAIN_PORT_DDI_C_LANES:

		return "PORT_DDI_C_LANES";

	case POWER_DOMAIN_PORT_DDI_D_LANES:

		return "PORT_DDI_D_LANES";

	case POWER_DOMAIN_PORT_DDI_E_LANES:

		return "PORT_DDI_E_LANES";

	case POWER_DOMAIN_PORT_DSI:

		return "PORT_DSI";

	case POWER_DOMAIN_PORT_CRT:

		return "PORT_CRT";

	case POWER_DOMAIN_PORT_OTHER:

		return "PORT_OTHER";

	case POWER_DOMAIN_VGA:

		return "VGA";

	case POWER_DOMAIN_AUDIO:

		return "AUDIO";

	case POWER_DOMAIN_PLLS:

		return "PLLS";

	case POWER_DOMAIN_AUX_A:

		return "AUX_A";

	case POWER_DOMAIN_AUX_B:

		return "AUX_B";

	case POWER_DOMAIN_AUX_C:

		return "AUX_C";

	case POWER_DOMAIN_AUX_D:

		return "AUX_D";

	case POWER_DOMAIN_GMBUS:

		return "GMBUS";

	case POWER_DOMAIN_MODESET:

		return "MODESET";

	case POWER_DOMAIN_INIT:

		return "INIT";

	default:

		MISSING_CASE(domain);

		return "?";

	}

}



static int i915_power_domain_info(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = m->private;
@@ -2775,7 +2709,7 @@ static int i915_power_domain_info(struct seq_file *m, void *unused) 
				continue;



			seq_printf(m, "  %-23s %d\n",

				 power_domain_str(power_domain),

				 intel_display_power_domain_str(power_domain),

				 power_domains->domain_use_count[power_domain]);

		}

	}

drivers/gpu/drm/i915/i915_drv.c

+73 −113
Original line number Diff line number Diff line
@@ -228,121 +228,83 @@ static const struct intel_device_info intel_sandybridge_m_info = { 
	.need_gfx_hws = 1, .has_hotplug = 1, \

	.has_fbc = 1, \

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \

	.has_llc = 1

	.has_llc = 1, \

	GEN_DEFAULT_PIPEOFFSETS, \

	IVB_CURSOR_OFFSETS



static const struct intel_device_info intel_ivybridge_d_info = {

	GEN7_FEATURES,

	.is_ivybridge = 1,

	GEN_DEFAULT_PIPEOFFSETS,

	IVB_CURSOR_OFFSETS,

};



static const struct intel_device_info intel_ivybridge_m_info = {

	GEN7_FEATURES,

	.is_ivybridge = 1,

	.is_mobile = 1,

	GEN_DEFAULT_PIPEOFFSETS,

	IVB_CURSOR_OFFSETS,

};



static const struct intel_device_info intel_ivybridge_q_info = {

	GEN7_FEATURES,

	.is_ivybridge = 1,

	.num_pipes = 0, /* legal, last one wins */

	GEN_DEFAULT_PIPEOFFSETS,

	IVB_CURSOR_OFFSETS,

};



#define VLV_FEATURES  \

	.gen = 7, .num_pipes = 2, \

	.need_gfx_hws = 1, .has_hotplug = 1, \

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \

	.display_mmio_offset = VLV_DISPLAY_BASE, \

	GEN_DEFAULT_PIPEOFFSETS, \

	CURSOR_OFFSETS



static const struct intel_device_info intel_valleyview_m_info = {

	GEN7_FEATURES,

	.is_mobile = 1,

	.num_pipes = 2,

	VLV_FEATURES,

	.is_valleyview = 1,

	.display_mmio_offset = VLV_DISPLAY_BASE,

	.has_fbc = 0, /* legal, last one wins */

	.has_llc = 0, /* legal, last one wins */

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

	.is_mobile = 1,

};



static const struct intel_device_info intel_valleyview_d_info = {

	GEN7_FEATURES,

	.num_pipes = 2,

	VLV_FEATURES,

	.is_valleyview = 1,

	.display_mmio_offset = VLV_DISPLAY_BASE,

	.has_fbc = 0, /* legal, last one wins */

	.has_llc = 0, /* legal, last one wins */

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};



#define HSW_FEATURES  \

	GEN7_FEATURES, \

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \

	.has_ddi = 1, \

	.has_fpga_dbg = 1



static const struct intel_device_info intel_haswell_d_info = {

	GEN7_FEATURES,

	HSW_FEATURES,

	.is_haswell = 1,

	.has_ddi = 1,

	.has_fpga_dbg = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,

	GEN_DEFAULT_PIPEOFFSETS,

	IVB_CURSOR_OFFSETS,

};



static const struct intel_device_info intel_haswell_m_info = {

	GEN7_FEATURES,

	HSW_FEATURES,

	.is_haswell = 1,

	.is_mobile = 1,

	.has_ddi = 1,

	.has_fpga_dbg = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,

	GEN_DEFAULT_PIPEOFFSETS,

	IVB_CURSOR_OFFSETS,

};



static const struct intel_device_info intel_broadwell_d_info = {

	.gen = 8, .num_pipes = 3,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,

	.has_llc = 1,

	.has_ddi = 1,

	.has_fpga_dbg = 1,

	.has_fbc = 1,

	GEN_DEFAULT_PIPEOFFSETS,

	IVB_CURSOR_OFFSETS,

	HSW_FEATURES,

	.gen = 8,

};



static const struct intel_device_info intel_broadwell_m_info = {

	.gen = 8, .is_mobile = 1, .num_pipes = 3,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,

	.has_llc = 1,

	.has_ddi = 1,

	.has_fpga_dbg = 1,

	.has_fbc = 1,

	GEN_DEFAULT_PIPEOFFSETS,

	IVB_CURSOR_OFFSETS,

	HSW_FEATURES,

	.gen = 8, .is_mobile = 1,

};



static const struct intel_device_info intel_broadwell_gt3d_info = {

	.gen = 8, .num_pipes = 3,

	.need_gfx_hws = 1, .has_hotplug = 1,

	HSW_FEATURES,

	.gen = 8,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,

	.has_llc = 1,

	.has_ddi = 1,

	.has_fpga_dbg = 1,

	.has_fbc = 1,

	GEN_DEFAULT_PIPEOFFSETS,

	IVB_CURSOR_OFFSETS,

};



static const struct intel_device_info intel_broadwell_gt3m_info = {

	.gen = 8, .is_mobile = 1, .num_pipes = 3,

	.need_gfx_hws = 1, .has_hotplug = 1,

	HSW_FEATURES,

	.gen = 8, .is_mobile = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,

	.has_llc = 1,

	.has_ddi = 1,

	.has_fpga_dbg = 1,

	.has_fbc = 1,

	GEN_DEFAULT_PIPEOFFSETS,

	IVB_CURSOR_OFFSETS,

};



static const struct intel_device_info intel_cherryview_info = {
@@ -356,29 +318,16 @@ static const struct intel_device_info intel_cherryview_info = { 
};



static const struct intel_device_info intel_skylake_info = {

	HSW_FEATURES,

	.is_skylake = 1,

	.gen = 9, .num_pipes = 3,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,

	.has_llc = 1,

	.has_ddi = 1,

	.has_fpga_dbg = 1,

	.has_fbc = 1,

	GEN_DEFAULT_PIPEOFFSETS,

	IVB_CURSOR_OFFSETS,

	.gen = 9,

};



static const struct intel_device_info intel_skylake_gt3_info = {

	HSW_FEATURES,

	.is_skylake = 1,

	.gen = 9, .num_pipes = 3,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.gen = 9,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,

	.has_llc = 1,

	.has_ddi = 1,

	.has_fpga_dbg = 1,

	.has_fbc = 1,

	GEN_DEFAULT_PIPEOFFSETS,

	IVB_CURSOR_OFFSETS,

};



static const struct intel_device_info intel_broxton_info = {
@@ -396,33 +345,18 @@ static const struct intel_device_info intel_broxton_info = { 
};



static const struct intel_device_info intel_kabylake_info = {

	HSW_FEATURES,

	.is_preliminary = 1,

	.is_kabylake = 1,

	.gen = 9,

	.num_pipes = 3,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,

	.has_llc = 1,

	.has_ddi = 1,

	.has_fpga_dbg = 1,

	.has_fbc = 1,

	GEN_DEFAULT_PIPEOFFSETS,

	IVB_CURSOR_OFFSETS,

};



static const struct intel_device_info intel_kabylake_gt3_info = {

	HSW_FEATURES,

	.is_preliminary = 1,

	.is_kabylake = 1,

	.gen = 9,

	.num_pipes = 3,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,

	.has_llc = 1,

	.has_ddi = 1,

	.has_fpga_dbg = 1,

	.has_fbc = 1,

	GEN_DEFAULT_PIPEOFFSETS,

	IVB_CURSOR_OFFSETS,

};



/*
@@ -465,6 +399,7 @@ static const struct pci_device_id pciidlist[] = { 
	INTEL_SKL_GT1_IDS(&intel_skylake_info),

	INTEL_SKL_GT2_IDS(&intel_skylake_info),

	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),

	INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),

	INTEL_BXT_IDS(&intel_broxton_info),

	INTEL_KBL_GT1_IDS(&intel_kabylake_info),

	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
@@ -565,7 +500,8 @@ void intel_detect_pch(struct drm_device *dev) 
				DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");

				WARN_ON(!IS_SKYLAKE(dev) &&

					!IS_KABYLAKE(dev));

			} else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE) {

			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||

				   (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE)) {

				dev_priv->pch_type = intel_virt_detect_pch(dev);

			} else

				continue;
@@ -624,6 +560,14 @@ static int vlv_resume_prepare(struct drm_i915_private *dev_priv, 
			      bool rpm_resume);

static int bxt_resume_prepare(struct drm_i915_private *dev_priv);



static bool suspend_to_idle(struct drm_i915_private *dev_priv)

{

#if IS_ENABLED(CONFIG_ACPI_SLEEP)

	if (acpi_target_system_state() < ACPI_STATE_S3)

		return true;

#endif

	return false;

}



static int i915_drm_suspend(struct drm_device *dev)

{
@@ -676,11 +620,7 @@ static int i915_drm_suspend(struct drm_device *dev) 


	i915_save_state(dev);



	opregion_target_state = PCI_D3cold;

#if IS_ENABLED(CONFIG_ACPI_SLEEP)

	if (acpi_target_system_state() < ACPI_STATE_S3)

		opregion_target_state = PCI_D1;

#endif

	opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;

	intel_opregion_notify_adapter(dev, opregion_target_state);



	intel_uncore_forcewake_reset(dev, false);
@@ -701,14 +641,25 @@ static int i915_drm_suspend(struct drm_device *dev) 
static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)

{

	struct drm_i915_private *dev_priv = drm_dev->dev_private;

	bool fw_csr;

	int ret;



	fw_csr = suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;

	/*

	 * In case of firmware assisted context save/restore don't manually

	 * deinit the power domains. This also means the CSR/DMC firmware will

	 * stay active, it will power down any HW resources as required and

	 * also enable deeper system power states that would be blocked if the

	 * firmware was inactive.

	 */

	if (!fw_csr)

		intel_power_domains_suspend(dev_priv);



	ret = intel_suspend_complete(dev_priv);



	if (ret) {

		DRM_ERROR("Suspend complete failed: %d\n", ret);

		if (!fw_csr)

			intel_power_domains_init_hw(dev_priv, true);



		return ret;
@@ -730,6 +681,8 @@ static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation) 
	if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))

		pci_set_power_state(drm_dev->pdev, PCI_D3hot);



	dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);



	return 0;

}
@@ -842,8 +795,10 @@ static int i915_drm_resume_early(struct drm_device *dev) 
	 * FIXME: This should be solved with a special hdmi sink device or

	 * similar so that power domains can be employed.

	 */

	if (pci_enable_device(dev->pdev))

		return -EIO;

	if (pci_enable_device(dev->pdev)) {

		ret = -EIO;

		goto out;

	}



	pci_set_master(dev->pdev);
@@ -861,8 +816,13 @@ static int i915_drm_resume_early(struct drm_device *dev) 
		hsw_disable_pc8(dev_priv);



	intel_uncore_sanitize(dev);



	if (!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))

		intel_power_domains_init_hw(dev_priv, true);



out:

	dev_priv->suspended_to_idle = false;



	return ret;

}

drivers/gpu/drm/i915/i915_drv.h

+50 −18
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ 


#define DRIVER_NAME		"i915"

#define DRIVER_DESC		"Intel Graphics"

#define DRIVER_DATE		"20151120"

#define DRIVER_DATE		"20151204"



#undef WARN_ON

/* Many gcc seem to no see through this and fall over :( */
@@ -902,7 +902,6 @@ struct i915_fbc { 
	/* This is always the inner lock when overlapping with struct_mutex and

	 * it's the outer lock when overlapping with stolen_lock. */

	struct mutex lock;

	unsigned long uncompressed_size;

	unsigned threshold;

	unsigned int fb_id;

	unsigned int possible_framebuffer_bits;
@@ -915,21 +914,21 @@ struct i915_fbc { 


	bool false_color;



	/* Tracks whether the HW is actually enabled, not whether the feature is

	 * possible. */

	bool enabled;

	bool active;



	struct intel_fbc_work {

		struct delayed_work work;

		struct intel_crtc *crtc;

		bool scheduled;

		struct work_struct work;

		struct drm_framebuffer *fb;

	} *fbc_work;

		unsigned long enable_jiffies;

	} work;



	const char *no_fbc_reason;



	bool (*fbc_enabled)(struct drm_i915_private *dev_priv);

	void (*enable_fbc)(struct intel_crtc *crtc);

	void (*disable_fbc)(struct drm_i915_private *dev_priv);

	bool (*is_active)(struct drm_i915_private *dev_priv);

	void (*activate)(struct intel_crtc *crtc);

	void (*deactivate)(struct drm_i915_private *dev_priv);

};



/**
@@ -1885,6 +1884,7 @@ struct drm_i915_private { 
	u32 chv_phy_control;



	u32 suspend_count;

	bool suspended_to_idle;

	struct i915_suspend_saved_registers regfile;

	struct vlv_s0ix_state vlv_s0ix_state;
@@ -2608,11 +2608,13 @@ struct drm_i915_cmd_table { 
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100

#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00

#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100

#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */



#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)

#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)

#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)

#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)

#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)

#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)

#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)

#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
@@ -2749,17 +2751,47 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); 
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,

				   uint32_t mask,

				   uint32_t bits);

void

ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);

void

ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);

void ilk_update_display_irq(struct drm_i915_private *dev_priv,

			    uint32_t interrupt_mask,

			    uint32_t enabled_irq_mask);

static inline void

ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)

{

	ilk_update_display_irq(dev_priv, bits, bits);

}

static inline void

ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)

{

	ilk_update_display_irq(dev_priv, bits, 0);

}

void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,

			 enum pipe pipe,

			 uint32_t interrupt_mask,

			 uint32_t enabled_irq_mask);

static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,

				       enum pipe pipe, uint32_t bits)

{

	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);

}

static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,

					enum pipe pipe, uint32_t bits)

{

	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);

}

void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,

				  uint32_t interrupt_mask,

				  uint32_t enabled_irq_mask);

#define ibx_enable_display_interrupt(dev_priv, bits) \

	ibx_display_interrupt_update((dev_priv), (bits), (bits))

#define ibx_disable_display_interrupt(dev_priv, bits) \

	ibx_display_interrupt_update((dev_priv), (bits), 0)

static inline void

ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)

{

	ibx_display_interrupt_update(dev_priv, bits, bits);

}

static inline void

ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)

{

	ibx_display_interrupt_update(dev_priv, bits, 0);

}





/* i915_gem.c */

int i915_gem_create_ioctl(struct drm_device *dev, void *data,

drivers/gpu/drm/i915/i915_gem.c

+1 −1
Original line number Diff line number Diff line
@@ -3077,7 +3077,7 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) 
		if (ret == 0)

			ret = __i915_wait_request(req[i], reset_counter, true,

						  args->timeout_ns > 0 ? &args->timeout_ns : NULL,

						  file->driver_priv);

						  to_rps_client(file));

		i915_gem_request_unreference__unlocked(req[i]);

	}

	return ret;

drivers/gpu/drm/i915/i915_gem_context.c

+0 −2
Original line number Diff line number Diff line
@@ -141,8 +141,6 @@ static void i915_gem_context_clean(struct intel_context *ctx) 
	if (!ppgtt)

		return;



	WARN_ON(!list_empty(&ppgtt->base.active_list));



	list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list,

				 mm_list) {

		if (WARN_ON(__i915_vma_unbind_no_wait(vma)))