Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 517e7610 authored by Vineet Gupta's avatar Vineet Gupta
Browse files

ARCv2: MCIP: update the BCR per current changes 



Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 36425cd6

arch/arc/kernel/mcip.c

+1 −2
Original line number Diff line number Diff line
@@ -93,11 +93,10 @@ static void mcip_probe_n_setup(void) 
	READ_BCR(ARC_REG_MCIP_BCR, mp);



	sprintf(smp_cpuinfo_buf,

		"Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s%s\n",

		"Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n",

		mp.ver, mp.num_cores,

		IS_AVAIL1(mp.ipi, "IPI "),

		IS_AVAIL1(mp.idu, "IDU "),

		IS_AVAIL1(mp.llm, "LLM "),

		IS_AVAIL1(mp.dbg, "DEBUG "),

		IS_AVAIL1(mp.gfrc, "GFRC"));

include/soc/arc/mcip.h

+8 −8
Original line number Diff line number Diff line
@@ -55,17 +55,17 @@ struct mcip_cmd { 


struct mcip_bcr {

#ifdef CONFIG_CPU_BIG_ENDIAN

		unsigned int pad3:8,

			     idu:1, llm:1, num_cores:6,

			     iocoh:1,  gfrc:1, dbg:1, pad2:1,

			     msg:1, sem:1, ipi:1, pad:1,

		unsigned int pad4:6, pw_dom:1, pad3:1,

			     idu:1, pad2:1, num_cores:6,

			     pad:1,  gfrc:1, dbg:1, pw:1,

			     msg:1, sem:1, ipi:1, slv:1,

			     ver:8;

#else

		unsigned int ver:8,

			     pad:1, ipi:1, sem:1, msg:1,

			     pad2:1, dbg:1, gfrc:1, iocoh:1,

			     num_cores:6, llm:1, idu:1,

			     pad3:8;

			     slv:1, ipi:1, sem:1, msg:1,

			     pw:1, dbg:1, gfrc:1, pad:1,

			     num_cores:6, pad2:1, idu:1,

			     pad3:1, pw_dom:1, pad4:6;

#endif

};