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Commit 51279ef9 authored by Sergej Sawazki's avatar Sergej Sawazki Committed by Stephen Boyd
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clk: si5351: Add DT property to enable PLL reset



Add optional output clock DT property to enable PLL reset when a clock
output is enabled.

Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: default avatarSergej Sawazki <sergej@taudac.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 758231d5
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+1 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ Optional child node properties:
- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
  divider.
- silabs,pll-master: boolean, multisynth can change pll frequency.
- silabs,pll-reset: boolean, clock output can reset its pll.
- silabs,disable-state : clock output disable state, shall be
  0 = clock output is driven LOW when disabled
  1 = clock output is driven HIGH when disabled
+3 −0
Original line number Diff line number Diff line
@@ -1297,6 +1297,9 @@ static int si5351_dt_parse(struct i2c_client *client,

		pdata->clkout[num].pll_master =
			of_property_read_bool(child, "silabs,pll-master");

		pdata->clkout[num].pll_reset =
			of_property_read_bool(child, "silabs,pll-reset");
	}
	client->dev.platform_data = pdata;

+2 −0
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ enum si5351_disable_state {
 * @multisynth_src: multisynth source clock
 * @clkout_src: clkout source clock
 * @pll_master: if true, clkout can also change pll rate
 * @pll_reset: if true, clkout can reset its pll
 * @drive: output drive strength
 * @rate: initial clkout rate, or default if 0
 */
@@ -95,6 +96,7 @@ struct si5351_clkout_config {
	enum si5351_drive_strength drive;
	enum si5351_disable_state disable_state;
	bool pll_master;
	bool pll_reset;
	unsigned long rate;
};