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Commit 5099fdd0 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "msm: ipa3: Increase constants for IPA register dump"

parents c1f6896d 9d45cb66

drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hw_common_ex.h

+210 −113
Original line number Diff line number Diff line
@@ -8,21 +8,17 @@ 
/* VLVL defs are available for 854 */

#define FEATURE_VLVL_DEFS                            true



/* IPAv4 version flag for Sdx24 */

#define FEATURE_IPA_HW_VERSION_4_0                   true

#define FEATURE_IPA_HW_VERSION_4_5                   true



/* Important Platform Specific Values : IRQ_NUM, IRQ_CNT, BCR */

#define IPA_HW_BAM_IRQ_NUM                           440

#define IPA_HW_BAM_IRQ_NUM                           639



/* Q6 IRQ number for IPA. */

#define IPA_HW_IRQ_NUM                               441

#define IPA_HW_IRQ_NUM                               640



/* Total number of different interrupts that can be enabled */

#define IPA_HW_IRQ_CNT_TOTAL                         23



/* IPAv4 BCR value */

#define IPA_HW_BCR_REG_VAL                           0x00000039



/* IPAv4 spare reg value */

#define IPA_HW_SPARE_1_REG_VAL                       0xC0000005
@@ -50,6 +46,8 @@ 


/* HPS Sequences */

#define IPA_HW_PKT_PROCESS_HPS_DMA                      0x0

#define IPA_HW_PKT_PROCESS_HPS_DMA_DECIPH_CIPHE         0x1

#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_NO_DECIPH_UCP    0x2

#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_UCP       0x3

#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_NO_DECIPH      0x4

#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_DECIPH         0x5
@@ -57,35 +55,48 @@ 
#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_NO_UCP    0x7

#define IPA_HW_PKT_PROCESS_HPS_DMA_PARSER               0x8

#define IPA_HW_PKT_PROCESS_HPS_DMA_DECIPH_PARSER        0x9

#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_UCP_TWICE_NO_DECIPH  0xA

#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_UCP_TWICE_DECIPH     0xB

#define IPA_HW_PKT_PROCESS_HPS_3_PKT_PRS_UCP_TWICE_NO_DECIPH  0xC

#define IPA_HW_PKT_PROCESS_HPS_3_PKT_PRS_UCP_TWICE_DECIPH     0xD



/* DPS Sequences */

#define IPA_HW_PKT_PROCESS_DPS_DMA                      0x0

#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECIPH          0x1

#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECOMP          0x2

#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_CIPH            0x3



/* Src RSRC GRP config */

#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_0           0x05050404

#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_1           0x0A0A0A0A

#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_2           0x0C0C0C0C

#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_0           0x0B040803

#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_1           0x0C0C0909

#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_2           0x0E0E0909

#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_3           0x3F003F00

#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_4           0x0E0E0E0E

#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_4           0x10101616



#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_0           0x00000101

#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_1           0x00000808

#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_2           0x00000808

#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_0           0x01010101

#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_1           0x02020202

#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_2           0x04040404

#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_3           0x3F003F00

#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_4           0x00000E0E

#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_4           0x02020606



#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_0           0x00000000

#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_1           0x00000000

#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_2           0x00000000

#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_3           0x00003F00

#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_4           0x00000000



/* Dest RSRC GRP config */

#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_0           0x04040404

#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_0           0x05051010

#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_1           0x3F013F02



#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_0           0x02020303

#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_1           0x02000201

#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_0           0x02020202

#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_1           0x02010201



#define IPA_HW_DST_RSRC_GRP_45_RSRC_TYPE_0           0x00000000

#define IPA_HW_DST_RSRC_GRP_45_RSRC_TYPE_1           0x00000200



#define IPA_HW_RX_HPS_CLIENTS_MIN_DEPTH_0            0x00020703

#define IPA_HW_RX_HPS_CLIENTS_MAX_DEPTH_0            0x00020703

#define IPA_HW_RX_HPS_CLIENTS_MIN_DEPTH_0            0x03030303

#define IPA_HW_RX_HPS_CLIENTS_MAX_DEPTH_0            0x03030303



#define IPA_HW_RSRP_GRP_0                            0x0

#define IPA_HW_RSRP_GRP_1                            0x1
@@ -98,8 +109,11 @@ 
#define IPA_HW_DDR_SRC_RSRP_GRP                      IPA_HW_RSRP_GRP_1

#define IPA_HW_DDR_DEST_RSRP_GRP                     IPA_HW_RSRP_GRP_1



#define IPA_HW_SRC_RSRP_TYPE_MAX                     0x4

#define IPA_HW_DST_RSRP_TYPE_MAX                     0x3

#define IPA_HW_DMA_SRC_RSRP_GRP                      IPA_HW_RSRP_GRP_2

#define IPA_HW_DMA_DEST_RSRP_GRP                     IPA_HW_RSRP_GRP_2



#define IPA_HW_SRC_RSRP_TYPE_MAX HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_MAXn

#define IPA_HW_DST_RSRP_TYPE_MAX HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_MAXn



#define GSI_HW_QSB_LOG_MISC_MAX 0x4
@@ -112,6 +126,9 @@ 
/* Whether to allow setting step mode on IPA when we crash or not */

#define IPA_HW_IS_STEP_MODE_ALLOWED                  (true)



/* Max number of virtual pipes for UL QBAP provided by HW */

#define IPA_HW_MAX_VP_NUM                             (32)



/*

 * HW specific clock vote freq values in KHz

 * (BIMC/SNOC/PCNOC/IPA/Q6 CPU)
@@ -137,11 +154,11 @@ enum ipa_hw_clk_freq_e { 
	IPA_HW_CLK_FREQ_SNOC_SVS_2      = 50000,



	/* IPA */

	IPA_HW_CLK_FREQ_IPA_PEAK        = 500000,

	IPA_HW_CLK_FREQ_IPA_NOM_PLUS    = 440000,

	IPA_HW_CLK_FREQ_IPA_NOM         = 440000,

	IPA_HW_CLK_FREQ_IPA_PEAK        = 600000,

	IPA_HW_CLK_FREQ_IPA_NOM_PLUS    = 500000,

	IPA_HW_CLK_FREQ_IPA_NOM         = 500000,

	IPA_HW_CLK_FREQ_IPA_SVS         = 250000,

	IPA_HW_CLK_FREQ_IPA_SVS_2       = 120000,

	IPA_HW_CLK_FREQ_IPA_SVS_2       = 150000,



	/* Q6 CPU */

	IPA_HW_CLK_FREQ_Q6_PEAK         = 729600,
@@ -150,6 +167,12 @@ enum ipa_hw_clk_freq_e { 
	IPA_HW_CLK_FREQ_Q6_SVS          = 729600,

};



enum ipa_hw_qtimer_gran_e {

	IPA_HW_QTIMER_GRAN_0 = 0, /* granularity 0 is 10us */

	IPA_HW_QTIMER_GRAN_1 = 1, /* granularity 1 is 100us */

	IPA_HW_QTIMER_GRAN_MAX,

};



/* Pipe ID of all the IPA pipes */

enum ipa_hw_pipe_id_e {

	IPA_HW_PIPE_ID_0,
@@ -175,35 +198,62 @@ enum ipa_hw_pipe_id_e { 
	IPA_HW_PIPE_ID_20,

	IPA_HW_PIPE_ID_21,

	IPA_HW_PIPE_ID_22,

	IPA_HW_PIPE_ID_23,

	IPA_HW_PIPE_ID_24,

	IPA_HW_PIPE_ID_25,

	IPA_HW_PIPE_ID_26,

	IPA_HW_PIPE_ID_27,

	IPA_HW_PIPE_ID_28,

	IPA_HW_PIPE_ID_29,

	IPA_HW_PIPE_ID_30,

	IPA_HW_PIPE_ID_MAX

};



/* Pipe ID's of System Bam Endpoints between Q6 & IPA */

enum ipa_hw_q6_pipe_id_e {

	/* Pipes used by IPA Q6 driver */

	IPA_HW_Q6_DL_CONSUMER_PIPE_ID           = IPA_HW_PIPE_ID_3,

	IPA_HW_Q6_CTL_CONSUMER_PIPE_ID          = IPA_HW_PIPE_ID_4,

	IPA_HW_Q6_UL_PRODUCER_PIPE_ID           = IPA_HW_PIPE_ID_13,

	IPA_HW_Q6_DL_PRODUCER_PIPE_ID           = IPA_HW_PIPE_ID_14,

	IPA_HW_Q6_DL_CONSUMER_PIPE_ID           = IPA_HW_PIPE_ID_5,

	IPA_HW_Q6_CTL_CONSUMER_PIPE_ID          = IPA_HW_PIPE_ID_6,

	IPA_HW_Q6_DL_NLO_CONSUMER_PIPE_ID       = IPA_HW_PIPE_ID_8,



	IPA_HW_Q6_UL_ACC_ACK_PRODUCER_PIPE_ID   = IPA_HW_PIPE_ID_20,

	IPA_HW_Q6_UL_PRODUCER_PIPE_ID           = IPA_HW_PIPE_ID_21,

	IPA_HW_Q6_DL_PRODUCER_PIPE_ID           = IPA_HW_PIPE_ID_17,

	IPA_HW_Q6_QBAP_STATUS_PRODUCER_PIPE_ID  = IPA_HW_PIPE_ID_18,

	IPA_HW_Q6_UL_ACC_DATA_PRODUCER_PIPE_ID  = IPA_HW_PIPE_ID_19,



	IPA_HW_Q6_UL_ACK_PRODUCER_PIPE_ID  =

	  IPA_HW_Q6_UL_ACC_ACK_PRODUCER_PIPE_ID,

	IPA_HW_Q6_UL_DATA_PRODUCER_PIPE_ID =

	  IPA_HW_Q6_UL_ACC_DATA_PRODUCER_PIPE_ID,



	IPA_HW_Q6_DMA_ASYNC_CONSUMER_PIPE_ID    = IPA_HW_PIPE_ID_4,

	IPA_HW_Q6_DMA_ASYNC_PRODUCER_PIPE_ID    = IPA_HW_PIPE_ID_29,



	IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_ID       = IPA_HW_PIPE_ID_6,

	IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_ID       = IPA_HW_PIPE_ID_16,

	/* Test Simulator Pipes */

	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_ID     = IPA_HW_PIPE_ID_0,

	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_ID     = IPA_HW_PIPE_ID_12,

	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_ID     = IPA_HW_PIPE_ID_1,

	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_ID     = IPA_HW_PIPE_ID_10,

	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_ID     = IPA_HW_PIPE_ID_2,

	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_ID     = IPA_HW_PIPE_ID_11,



	/* GSI UT channel SW->IPA */

	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_ID     = IPA_HW_PIPE_ID_5,

	/* GSI UT channel IPA->SW */

	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_ID     = IPA_HW_PIPE_ID_17,

	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_ID     = IPA_HW_PIPE_ID_3,

	/* GSI UT channel SW->IPA */

	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_ID     = IPA_HW_PIPE_ID_7,

	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_ID     = IPA_HW_PIPE_ID_10,



	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_ID     = IPA_HW_PIPE_ID_7,



	/* GSI UT channel IPA->SW */

	IPA_HW_Q6_DIAG_CONSUMER_PIPE_ID         = IPA_HW_PIPE_ID_9,



	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_ID     = IPA_HW_PIPE_ID_23,

	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_ID     = IPA_HW_PIPE_ID_24,



	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_ID     = IPA_HW_PIPE_ID_25,



	/* GSI UT channel IPA->SW */

	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_ID     = IPA_HW_PIPE_ID_26,



	/* GSI UT channel IPA->SW */

	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_ID     = IPA_HW_PIPE_ID_18,

	IPA_HW_Q6_DIAG_CONSUMER_PIPE_ID         = IPA_HW_PIPE_ID_19,

	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_ID     = IPA_HW_PIPE_ID_27,

	IPA_HW_Q6_PIPE_ID_MAX                   = IPA_HW_PIPE_ID_MAX,

};
@@ -211,26 +261,32 @@ enum ipa_hw_q6_pipe_ch_id_e { 
	/* Channels used by IPA Q6 driver */

	IPA_HW_Q6_DL_CONSUMER_PIPE_CH_ID                = 0,

	IPA_HW_Q6_CTL_CONSUMER_PIPE_CH_ID               = 1,

	IPA_HW_Q6_UL_PRODUCER_PIPE_CH_ID           = 3,

	IPA_HW_Q6_DL_PRODUCER_PIPE_CH_ID           = 4,

	IPA_HW_Q6_DL_NLO_CONSUMER_PIPE_CH_ID            = 2,

	IPA_HW_Q6_UL_ACC_PATH_ACK_PRODUCER_PIPE_CH_ID   = 6,

	IPA_HW_Q6_UL_PRODUCER_PIPE_CH_ID                = 7,

	IPA_HW_Q6_DL_PRODUCER_PIPE_CH_ID                = 3,

	IPA_HW_Q6_UL_ACC_PATH_DATA_PRODUCER_PIPE_CH_ID  = 5,

	IPA_HW_Q6_QBAP_STATUS_PRODUCER_PIPE_CH_ID       = 4,



	IPA_HW_Q6_DMA_ASYNC_CONSUMER_PIPE_CH_ID         = 8,

	IPA_HW_Q6_DMA_ASYNC_PRODUCER_PIPE_CH_ID         = 9,

	/* CH_ID 8 and 9 are Q6 SPARE CONSUMERs */



	IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_CH_ID       = 2,

	IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_CH_ID       = 5,

	/* Test Simulator Channels */

	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_CH_ID     = 6,

	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_CH_ID     = 8,

	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_CH_ID     = 9,

	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_CH_ID     = 10,

	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_CH_ID     = 11,

	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_CH_ID     = 12,

	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_CH_ID     = 10,

	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_CH_ID     = 11,

	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_CH_ID     = 12,

	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_CH_ID     = 13,

	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_CH_ID     = 14,

	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_CH_ID     = 15,

	/* GSI UT channel SW->IPA */

	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_CH_ID     = 13,

	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_CH_ID     = 16,

	/* GSI UT channel IPA->SW */

	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_CH_ID     = 14,

	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_CH_ID     = 17,

	/* GSI UT channel SW->IPA */

	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_CH_ID     = 15,

	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_CH_ID     = 18,

	/* GSI UT channel IPA->SW */

	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_CH_ID     = 16,

	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_CH_ID     = 19,

};



/* System Bam Endpoints between Q6 & IPA */
@@ -243,33 +299,42 @@ enum ipa_hw_q6_pipe_e { 
	IPA_HW_Q6_DL_CONSUMER_PIPE = 2,

	/* CTL Pipe Q6->IPA */

	IPA_HW_Q6_CTL_CONSUMER_PIPE = 3,

	/*  Q6 -> IPA,  LTE DL Optimized path */

	IPA_HW_Q6_LTE_DL_CONSUMER_PIPE = 4,

	/* LWA DL(Wifi to Q6) */

	IPA_HW_Q6_LWA_DL_PRODUCER_PIPE = 5,

	/*  Q6 -> IPA,  DL NLO  */

	IPA_HW_Q6_DL_NLO_CONSUMER_PIPE = 4,

	/* DMA ASYNC CONSUMER */

	IPA_HW_Q6_DMA_ASYNC_CONSUMER_PIPE = 5,

	/* DMA ASYNC PRODUCER */

	IPA_HW_Q6_DMA_ASYNC_PRODUCER_PIPE = 6,

	/* UL Acc Path Data Pipe IPA->Q6 */

	IPA_HW_Q6_UL_ACC_DATA_PRODUCER_PIPE = 7,

	/* UL Acc Path ACK Pipe IPA->Q6 */

	IPA_HW_Q6_UL_ACC_ACK_PRODUCER_PIPE = 8,

	/* UL Acc Path QBAP status Pipe IPA->Q6 */

	IPA_HW_Q6_QBAP_STATUS_PRODUCER_PIPE = 9,

	/* Diag status pipe IPA->Q6 */

	/* Used only when FEATURE_IPA_TEST_PER_SIM is ON */

	/* SIM Pipe IPA->Sim */

	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0 = 7,

	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0 = 10,

	/* SIM Pipe Sim->IPA */

	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1 = 8,

	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1 = 11,

	/* SIM Pipe Sim->IPA */

	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2 = 9,

	IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2 = 12,

	/* SIM Pipe Sim->IPA */

	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0 = 10,

	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0 = 13,

	/* SIM B2B PROD Pipe  */

	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1 = 11,

	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1 = 14,

	/* SIM Pipe IPA->Sim */

	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2 = 12,

	IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2 = 15,

	/* End FEATURE_IPA_TEST_PER_SIM */

	/* GSI UT channel SW->IPA */

	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1 = 13,

	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1 = 16,

	/* GSI UT channel IPA->SW */

	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1 = 14,

	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1 = 17,

	/* GSI UT channel SW->IPA */

	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2 = 15,

	IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2 = 18,

	/* GSI UT channel IPA->SW */

	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2 = 16,

	IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2 = 19,



	IPA_HW_Q6_PIPE_TOTAL

};
@@ -375,12 +440,7 @@ enum ipa_hw_irq_srcs_e { 
/*

 * Total number of channel contexts that need to be saved for APPS

 */

#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7          14



/*

 * Total number of channel contexts that need to be saved for Q6

 */

#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6          6

#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7          19



/*

 * Total number of channel contexts that need to be saved for UC
@@ -390,12 +450,7 @@ enum ipa_hw_irq_srcs_e { 
/*

 * Total number of event ring contexts that need to be saved for APPS

 */

#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7         12



/*

 * Total number of event ring contexts that need to be saved for Q6

 */

#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_Q6         4

#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7         19



/*

 * Total number of event ring contexts that need to be saved for UC
@@ -413,38 +468,12 @@ enum ipa_hw_irq_srcs_e { 
 * Total number of endpoints for which ipa_reg_save.pipes[endp_number]

 * are always saved

 */

#define IPA_HW_REG_SAVE_NUM_ACTIVE_PIPES             23

#define IPA_HW_REG_SAVE_NUM_ACTIVE_PIPES             IPA_HW_PIPE_ID_MAX



/*

 * Macro to set the active flag for all active pipe indexed register

 * SHRAM Bytes per ch

 */

#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_ACTIVE() \

	do { \

		ipa_reg_save.ipa.pipes[0].active = true; \

		ipa_reg_save.ipa.pipes[1].active = true; \

		ipa_reg_save.ipa.pipes[2].active = true; \

		ipa_reg_save.ipa.pipes[3].active = true; \

		ipa_reg_save.ipa.pipes[4].active = true; \

		ipa_reg_save.ipa.pipes[5].active = true; \

		ipa_reg_save.ipa.pipes[6].active = true; \

		ipa_reg_save.ipa.pipes[7].active = true; \

		ipa_reg_save.ipa.pipes[8].active = true; \

		ipa_reg_save.ipa.pipes[9].active = true; \

		ipa_reg_save.ipa.pipes[10].active = true; \

		ipa_reg_save.ipa.pipes[11].active = true; \

		ipa_reg_save.ipa.pipes[12].active = true; \

		ipa_reg_save.ipa.pipes[13].active = true; \

		ipa_reg_save.ipa.pipes[14].active = true; \

		ipa_reg_save.ipa.pipes[15].active = true; \

		ipa_reg_save.ipa.pipes[16].active = true; \

		ipa_reg_save.ipa.pipes[17].active = true; \

		ipa_reg_save.ipa.pipes[18].active = true; \

		ipa_reg_save.ipa.pipes[19].active = true; \

		ipa_reg_save.ipa.pipes[20].active = true; \

		ipa_reg_save.ipa.pipes[21].active = true; \

		ipa_reg_save.ipa.pipes[22].active = true; \

	} while (0)



#define IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM         12



/*

 * Total number of rx splt cmdq's see:
@@ -452,6 +481,74 @@ enum ipa_hw_irq_srcs_e { 
 */

#define IPA_RX_SPLT_CMDQ_MAX 4



/*

 * Macro to define a particular register cfg entry for all pipe

 * indexed register

 */

#define IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(reg_name, var_name)	\

	{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \

		(u32 *)&ipa_reg_save.ipa.pipes[0].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \

		(u32 *)&ipa_reg_save.ipa.pipes[1].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 2), \

		(u32 *)&ipa_reg_save.ipa.pipes[2].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 3), \

		(u32 *)&ipa_reg_save.ipa.pipes[3].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 4), \

		(u32 *)&ipa_reg_save.ipa.pipes[4].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 5), \

		(u32 *)&ipa_reg_save.ipa.pipes[5].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 6), \

		(u32 *)&ipa_reg_save.ipa.pipes[6].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 7), \

		(u32 *)&ipa_reg_save.ipa.pipes[7].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 8), \

		(u32 *)&ipa_reg_save.ipa.pipes[8].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 9), \

		(u32 *)&ipa_reg_save.ipa.pipes[9].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 10), \

		(u32 *)&ipa_reg_save.ipa.pipes[10].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 11), \

		(u32 *)&ipa_reg_save.ipa.pipes[11].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 12), \

		(u32 *)&ipa_reg_save.ipa.pipes[12].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 13), \

		(u32 *)&ipa_reg_save.ipa.pipes[13].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 14), \

		(u32 *)&ipa_reg_save.ipa.pipes[14].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 15), \

		(u32 *)&ipa_reg_save.ipa.pipes[15].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 16), \

		(u32 *)&ipa_reg_save.ipa.pipes[16].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 17), \

		(u32 *)&ipa_reg_save.ipa.pipes[17].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 18), \

		(u32 *)&ipa_reg_save.ipa.pipes[18].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 19), \

		(u32 *)&ipa_reg_save.ipa.pipes[19].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 20), \

		(u32 *)&ipa_reg_save.ipa.pipes[20].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 21), \

		(u32 *)&ipa_reg_save.ipa.pipes[21].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 22), \

		(u32 *)&ipa_reg_save.ipa.pipes[22].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 23), \

		(u32 *)&ipa_reg_save.ipa.pipes[23].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 24), \

		(u32 *)&ipa_reg_save.ipa.pipes[24].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 25), \

		(u32 *)&ipa_reg_save.ipa.pipes[25].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 26), \

		(u32 *)&ipa_reg_save.ipa.pipes[26].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 27), \

		(u32 *)&ipa_reg_save.ipa.pipes[27].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 28), \

		(u32 *)&ipa_reg_save.ipa.pipes[28].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 29), \

		(u32 *)&ipa_reg_save.ipa.pipes[29].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 30), \

		(u32 *)&ipa_reg_save.ipa.pipes[30].endp.var_name }



/*

 * Macro to define a particular register cfg entry for the remaining

 * pipe indexed register.  In Stingray case we don't have extra

drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hwio.h

+55 −10
Original line number Diff line number Diff line
@@ -974,12 +974,21 @@ 
	out_dword( \

		HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR(n), \

		val)

#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_OUTMI(n, mask, val) \

		out_dword_masked_ns( \

			HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR(n), \

#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_OUTMI(n, mask, \

					      val) out_dword_masked_ns(	\

		HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR( \

			n), \

		mask, \

		val, \

		HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INI(n))

#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_3_BMSK 0xff000000

#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_3_SHFT 0x18

#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_2_BMSK 0xff0000

#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_2_SHFT 0x10

#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_1_BMSK 0xff00

#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_1_SHFT 0x8

#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_0_BMSK 0xff

#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INST_BYTE_0_SHFT 0x0

#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + \

					      0x00002000 + 0x4 * (n))

#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_PHYS(n) ( \
@@ -7404,11 +7413,47 @@ 
					  0x0000038c)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \

					  0x0000038c)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_RMSK 0x1f

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ATTR 0x3

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_IN in_dword_masked(	\

		HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, \

		HWIO_IPA_RX_HPS_CMDQ_CFG_WR_RMSK)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_INM(m) in_dword_masked( \

		HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, \

		m)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OUT(v) out_dword( \

		HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, \

		v)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OUTM(m, v) out_dword_masked_ns( \

		HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, \

		m, \

		v, \

		HWIO_IPA_RX_HPS_CMDQ_CFG_WR_IN)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_BLOCK_WR_BMSK 0x1f

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_BLOCK_WR_SHFT 0x0

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000390)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \

					  0x00000390)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \

					  0x00000390)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_RMSK 0x1f

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ATTR 0x3

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_IN in_dword_masked(	\

		HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, \

		HWIO_IPA_RX_HPS_CMDQ_CFG_RD_RMSK)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_INM(m) in_dword_masked( \

		HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, \

		m)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OUT(v) out_dword( \

		HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, \

		v)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OUTM(m, v) out_dword_masked_ns( \

		HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, \

		m, \

		v, \

		HWIO_IPA_RX_HPS_CMDQ_CFG_RD_IN)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_BLOCK_RD_BMSK 0x1f

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_BLOCK_RD_SHFT 0x0

#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \

					     0x00000394)

#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \

drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hwio_def.h

+16 −0
Original line number Diff line number Diff line
@@ -1941,6 +1941,22 @@ union ipa_hwio_def_ipa_rx_hps_cmdq_cmd_u { 
	struct ipa_hwio_def_ipa_rx_hps_cmdq_cmd_s	def;

	u32						value;

};

struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_s {

	u32	block_wr : 5;

	u32	reserved0 : 27;

};

union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_u {

	struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_s	def;

	u32						value;

};

struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_s {

	u32	block_rd : 5;

	u32	reserved0 : 27;

};

union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_u {

	struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_s	def;

	u32						value;

};

struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_s {

	u32	cmdq_packet_len_f : 16;

	u32	cmdq_dest_len_f : 16;

drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c

+15 −24
Original line number Diff line number Diff line
@@ -246,7 +246,12 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = { 
	IPA_REG_SAVE_RX_SPLT_CMDQ(

		IPA_RX_SPLT_CMDQ_STATUS_n, ipa_rx_splt_cmdq_status_n),





	GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_CFG_WR,

				  ipa.dbg,

				  ipa_rx_hps_cmdq_cfg_wr),

	GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_CFG_RD,

				  ipa.dbg,

				  ipa_rx_hps_cmdq_cfg_rd),

	GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_CMD,

			     ipa.dbg,

			     ipa_rx_hps_cmdq_cmd),
@@ -731,9 +736,11 @@ static void out_dword( 
 */

void ipa_save_gsi_ver(void)

{

	if (!ipa3_ctx->do_register_collection_on_crash)

		return;



	ipa_reg_save.gsi.fw_ver =

		IPA_READ_1xVECTOR_REG(IPA_GSI_TOP_GSI_INST_RAM_n, 0) &

		0x0000FFFF;

		IPA_READ_1xVECTOR_REG(IPA_GSI_TOP_GSI_INST_RAM_n, 0);

}



/*
@@ -775,7 +782,11 @@ void ipa_save_registers(void) 
			in_dword(ipa_regs_to_save_array[i].src_addr);

	}



	IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_ACTIVE();

	/*

	 * Set the active flag for all active pipe indexed registers.

	 */

	for (i = 0; i < IPA_HW_PIPE_ID_MAX; i++)

		ipa_reg_save.ipa.pipes[i].active = true;



	/* Now save the per endp registers for the remaining pipes */

	for (i = 0; i < (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS *
@@ -864,26 +875,6 @@ void ipa_save_registers(void) 
				n + IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM - 1);

	}



	for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6; i++) {

		u32 phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.q6[

			i].gsi_map_ee_n_ch_k_vp_table.phy_ch;

		u32 n = phys_ch_idx*IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM;



		if (!ipa_reg_save.gsi.ch_cntxt.q6[

				i].gsi_map_ee_n_ch_k_vp_table.valid)

			continue;

		ipa_reg_save.gsi.ch_cntxt.q6[

			i].mcs_channel_scratch.scratch4.shram =

			IPA_READ_1xVECTOR_REG(

				GSI_SHRAM_n,

				n + IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM - 2);

		ipa_reg_save.gsi.ch_cntxt.q6[

			i].mcs_channel_scratch.scratch5.shram =

			IPA_READ_1xVECTOR_REG(

				GSI_SHRAM_n,

				n + IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM - 1);

	}



	for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC; i++) {

		u32 phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.uc[

			i].gsi_map_ee_n_ch_k_vp_table.phy_ch;

drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h

+30 −79

File changed.

Preview size limit exceeded, changes collapsed.