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Commit 50812f7f authored by Satya Durga Srinivasu Prabhala's avatar Satya Durga Srinivasu Prabhala
Browse files

ARM: dts: msm: add dynamic-power-coefficient property for Kona 



The "dynamic-power-coefficient" in DT is used to build Energy Model
which in turn used by EAS to take placement decisions.

Change-Id: If22d0bcb053d7878c61ac2b7030de1161a289a09
Signed-off-by: default avatarSatya Durga Srinivasu Prabhala <satyap@codeaurora.org>
parent 12dec36c

arch/arm64/boot/dts/qcom/kona.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ 
			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -72,6 +73,7 @@ 
			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -90,6 +92,7 @@ 
			next-level-cache = <&L2_2>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			L2_2: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -108,6 +111,7 @@ 
			next-level-cache = <&L2_3>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			L2_3: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -126,6 +130,7 @@ 
			next-level-cache = <&L2_4>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			capacity-dmips-mhz = <1894>;

			dynamic-power-coefficient = <374>;

			L2_4: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -144,6 +149,7 @@ 
			next-level-cache = <&L2_5>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			capacity-dmips-mhz = <1894>;

			dynamic-power-coefficient = <374>;

			L2_5: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -162,6 +168,7 @@ 
			next-level-cache = <&L2_6>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			capacity-dmips-mhz = <1894>;

			dynamic-power-coefficient = <374>;

			L2_6: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -180,6 +187,7 @@ 
			next-level-cache = <&L2_7>;

			qcom,freq-domain = <&cpufreq_hw 2 4>;

			capacity-dmips-mhz = <1894>;

			dynamic-power-coefficient = <431>;

			L2_7: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x80000>;