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Commit 507d44a9 authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'drm-intel-next-2016-02-29' of git://anongit.freedesktop.org/drm-intel into drm-next 

- fbc by default on hsw&bdw, thanks to great work by Paulo!
- psr by default hsw,bdw,vlv&chv, thanks to great work by Rodrigo!
- fixes to hw state readout vs. rpm issues (Imre)
- dc3 fixes&improvements (Mika), this and above already cherr-pick to -fixes
- first part of locking fixes from Tvrtko
- proper atomic code for load detect (Maarten)
- more rpm fixes from Ville
- more atomic work from Maarten

* tag 'drm-intel-next-2016-02-29' of git://anongit.freedesktop.org/drm-intel: (63 commits)
  drm/i915: Update DRIVER_DATE to 20160229
  drm/i915: Execlists cannot pin a context without the object
  drm/i915: Reduce the pointer dance of i915_is_ggtt()
  drm/i915: Rename vma->*_list to *_link for consistency
  drm/i915: Balance assert_rpm_wakelock_held() for !IS_ENABLED(CONFIG_PM)
  drm/i915/lrc: Only set RS ctx enable in ctx control reg if there is a RS
  drm/i915/gen9: Set value of Indirect Context Offset based on gen version
  drm/i915: Remove update_sprite_watermarks.
  drm/i915: Kill off intel_crtc->atomic.wait_vblank, v6.
  drm/i915: Unify power domain handling.
  drm/i915: Pass crtc state to modeset_get_crtc_power_domains.
  drm/i915: Add for_each_pipe_masked()
  drm/i915: Make sure pipe interrupts are processed before turning off power well on BDW+
  drm/i915: synchronize_irq() before turning off disp2d power well on VLV/CHV
  drm/i915: Skip PIPESTAT reads from irq handler on VLV/CHV when power well is down
  drm/i915/gen9: Write dc state debugmask bits only once
  drm/i915/gen9: Extend dmc debug mask to include cores
  drm/i915/gen9: Verify and enforce dc6 state writes
  drm/i915/gen9: Check for DC state mismatch
  drm/i915/fbc: enable FBC by default on HSW and BDW
  ...
parents d8c61663 5790ff74

drivers/gpu/drm/i915/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -45,3 +45,14 @@ config DRM_I915_PRELIMINARY_HW_SUPPORT 
	  option changes the default for that module option.



	  If in doubt, say "N".



config DRM_I915_USERPTR

	bool "Always enable userptr support"

	depends on DRM_I915

	select MMU_NOTIFIER

	default y

	help

	  This option selects CONFIG_MMU_NOTIFIER if it isn't already

	  selected to enabled full userptr support.



	  If in doubt, say "Y".

drivers/gpu/drm/i915/i915_debugfs.c

+34 −22
Original line number Diff line number Diff line
@@ -117,9 +117,8 @@ static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) 
	u64 size = 0;

	struct i915_vma *vma;



	list_for_each_entry(vma, &obj->vma_list, vma_link) {

		if (i915_is_ggtt(vma->vm) &&

		    drm_mm_node_allocated(&vma->node))

	list_for_each_entry(vma, &obj->vma_list, obj_link) {

		if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))

			size += vma->node.size;

	}
@@ -155,7 +154,7 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 
		   obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");

	if (obj->base.name)

		seq_printf(m, " (name: %d)", obj->base.name);

	list_for_each_entry(vma, &obj->vma_list, vma_link) {

	list_for_each_entry(vma, &obj->vma_list, obj_link) {

		if (vma->pin_count > 0)

			pin_count++;

	}
@@ -164,13 +163,12 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 
		seq_printf(m, " (display)");

	if (obj->fence_reg != I915_FENCE_REG_NONE)

		seq_printf(m, " (fence: %d)", obj->fence_reg);

	list_for_each_entry(vma, &obj->vma_list, vma_link) {

	list_for_each_entry(vma, &obj->vma_list, obj_link) {

		seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",

			   i915_is_ggtt(vma->vm) ? "g" : "pp",

			   vma->is_ggtt ? "g" : "pp",

			   vma->node.start, vma->node.size);

		if (i915_is_ggtt(vma->vm))

			seq_printf(m, ", type: %u)", vma->ggtt_view.type);

		else

		if (vma->is_ggtt)

			seq_printf(m, ", type: %u", vma->ggtt_view.type);

		seq_puts(m, ")");

	}

	if (obj->stolen)
@@ -230,7 +228,7 @@ static int i915_gem_object_list_info(struct seq_file *m, void *data) 
	}



	total_obj_size = total_gtt_size = count = 0;

	list_for_each_entry(vma, head, mm_list) {

	list_for_each_entry(vma, head, vm_link) {

		seq_printf(m, "   ");

		describe_obj(m, vma->obj);

		seq_printf(m, "\n");
@@ -342,13 +340,13 @@ static int per_file_stats(int id, void *ptr, void *data) 
		stats->shared += obj->base.size;



	if (USES_FULL_PPGTT(obj->base.dev)) {

		list_for_each_entry(vma, &obj->vma_list, vma_link) {

		list_for_each_entry(vma, &obj->vma_list, obj_link) {

			struct i915_hw_ppgtt *ppgtt;



			if (!drm_mm_node_allocated(&vma->node))

				continue;



			if (i915_is_ggtt(vma->vm)) {

			if (vma->is_ggtt) {

				stats->global += obj->base.size;

				continue;

			}
@@ -454,12 +452,12 @@ static int i915_gem_object_info(struct seq_file *m, void* data) 
		   count, mappable_count, size, mappable_size);



	size = count = mappable_size = mappable_count = 0;

	count_vmas(&vm->active_list, mm_list);

	count_vmas(&vm->active_list, vm_link);

	seq_printf(m, "  %u [%u] active objects, %llu [%llu] bytes\n",

		   count, mappable_count, size, mappable_size);



	size = count = mappable_size = mappable_count = 0;

	count_vmas(&vm->inactive_list, mm_list);

	count_vmas(&vm->inactive_list, vm_link);

	seq_printf(m, "  %u [%u] inactive objects, %llu [%llu] bytes\n",

		   count, mappable_count, size, mappable_size);
@@ -825,8 +823,11 @@ static int i915_interrupt_info(struct seq_file *m, void *data) 
		}



		for_each_pipe(dev_priv, pipe) {

			if (!intel_display_power_is_enabled(dev_priv,

						POWER_DOMAIN_PIPE(pipe))) {

			enum intel_display_power_domain power_domain;



			power_domain = POWER_DOMAIN_PIPE(pipe);

			if (!intel_display_power_get_if_enabled(dev_priv,

								power_domain)) {

				seq_printf(m, "Pipe %c power disabled\n",

					   pipe_name(pipe));

				continue;
@@ -840,6 +841,8 @@ static int i915_interrupt_info(struct seq_file *m, void *data) 
			seq_printf(m, "Pipe %c IER:\t%08x\n",

				   pipe_name(pipe),

				   I915_READ(GEN8_DE_PIPE_IER(pipe)));



			intel_display_power_put(dev_priv, power_domain);

		}



		seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
@@ -4004,6 +4007,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, 
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];

	struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,

									pipe));

	enum intel_display_power_domain power_domain;

	u32 val = 0; /* shut up gcc */

	int ret;
@@ -4014,7 +4018,8 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, 
	if (pipe_crc->source && source)

		return -EINVAL;



	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {

	power_domain = POWER_DOMAIN_PIPE(pipe);

	if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {

		DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");

		return -EIO;

	}
@@ -4031,7 +4036,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, 
		ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);



	if (ret != 0)

		return ret;

		goto out;



	/* none -> real source transition */

	if (source) {
@@ -4043,8 +4048,10 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, 
		entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,

				  sizeof(pipe_crc->entries[0]),

				  GFP_KERNEL);

		if (!entries)

			return -ENOMEM;

		if (!entries) {

			ret = -ENOMEM;

			goto out;

		}



		/*

		 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
@@ -4100,7 +4107,12 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, 
		hsw_enable_ips(crtc);

	}



	return 0;

	ret = 0;



out:

	intel_display_power_put(dev_priv, power_domain);



	return ret;

}



/*

drivers/gpu/drm/i915/i915_dma.c

+2 −2
Original line number Diff line number Diff line
@@ -444,8 +444,8 @@ static int i915_load_modeset_init(struct drm_device *dev) 


cleanup_gem:

	mutex_lock(&dev->struct_mutex);

	i915_gem_cleanup_ringbuffer(dev);

	i915_gem_context_fini(dev);

	i915_gem_cleanup_engines(dev);

	mutex_unlock(&dev->struct_mutex);

cleanup_irq:

	intel_guc_ucode_fini(dev);
@@ -1256,8 +1256,8 @@ int i915_driver_unload(struct drm_device *dev) 


	intel_guc_ucode_fini(dev);

	mutex_lock(&dev->struct_mutex);

	i915_gem_cleanup_ringbuffer(dev);

	i915_gem_context_fini(dev);

	i915_gem_cleanup_engines(dev);

	mutex_unlock(&dev->struct_mutex);

	intel_fbc_cleanup_cfb(dev_priv);

drivers/gpu/drm/i915/i915_drv.c

+0 −8
Original line number Diff line number Diff line
@@ -603,13 +603,7 @@ static int i915_drm_suspend(struct drm_device *dev) 


	intel_suspend_gt_powersave(dev);



	/*

	 * Disable CRTCs directly since we want to preserve sw state

	 * for _thaw. Also, power gate the CRTC power wells.

	 */

	drm_modeset_lock_all(dev);

	intel_display_suspend(dev);

	drm_modeset_unlock_all(dev);



	intel_dp_mst_suspend(dev);
@@ -764,9 +758,7 @@ static int i915_drm_resume(struct drm_device *dev) 
		dev_priv->display.hpd_irq_setup(dev);

	spin_unlock_irq(&dev_priv->irq_lock);



	drm_modeset_lock_all(dev);

	intel_display_resume(dev);

	drm_modeset_unlock_all(dev);



	intel_dp_mst_resume(dev);

drivers/gpu/drm/i915/i915_drv.h

+7 −9
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ 


#define DRIVER_NAME		"i915"

#define DRIVER_DESC		"Intel Graphics"

#define DRIVER_DATE		"20160214"

#define DRIVER_DATE		"20160229"



#undef WARN_ON

/* Many gcc seem to no see through this and fall over :( */
@@ -261,6 +261,9 @@ struct i915_hotplug { 


#define for_each_pipe(__dev_priv, __p) \

	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)

#define for_each_pipe_masked(__dev_priv, __p, __mask) \

	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \

		for_each_if ((__mask) & (1 << (__p)))

#define for_each_plane(__dev_priv, __pipe, __p)				\

	for ((__p) = 0;							\

	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
@@ -746,6 +749,7 @@ struct intel_csr { 
	uint32_t mmio_count;

	i915_reg_t mmioaddr[8];

	uint32_t mmiodata[8];

	uint32_t dc_state;

};



#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
@@ -1848,6 +1852,7 @@ struct drm_i915_private { 


	enum modeset_restore modeset_restore;

	struct mutex modeset_restore_lock;

	struct drm_atomic_state *modeset_restore_state;



	struct list_head vm_list; /* Global list of all address spaces */

	struct i915_gtt gtt; /* VM representing the global address space */
@@ -3058,7 +3063,7 @@ int i915_gem_init_rings(struct drm_device *dev); 
int __must_check i915_gem_init_hw(struct drm_device *dev);

int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);

void i915_gem_init_swizzling(struct drm_device *dev);

void i915_gem_cleanup_engines(struct drm_device *dev);

void i915_gem_cleanup_ringbuffer(struct drm_device *dev);

int __must_check i915_gpu_idle(struct drm_device *dev);

int __must_check i915_gem_suspend(struct drm_device *dev);

void __i915_add_request(struct drm_i915_gem_request *req,
@@ -3151,18 +3156,11 @@ bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj); 
/* Some GGTT VM helpers */

#define i915_obj_to_ggtt(obj) \

	(&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)

static inline bool i915_is_ggtt(struct i915_address_space *vm)

{

	struct i915_address_space *ggtt =

		&((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;

	return vm == ggtt;

}



static inline struct i915_hw_ppgtt *

i915_vm_to_ppgtt(struct i915_address_space *vm)

{

	WARN_ON(i915_is_ggtt(vm));



	return container_of(vm, struct i915_hw_ppgtt, base);

}