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Commit 5034b1fa authored by Tomi Valkeinen's avatar Tomi Valkeinen
Browse files

drm/omap: remove all EXPORT_SYMBOLs from dispc.c 



omapdrm now uses dispc_ops instead of direct function calls so we can
remove all EXPORT_SYMBOLs from dispc. Most of the functions can also be
made static, but a few are used outside dispc.c.

Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
parent 9f759225

drivers/gpu/drm/omapdrm/dss/dispc.c

+30 −54
Original line number Diff line number Diff line
@@ -306,6 +306,10 @@ static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel); 
static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);

static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);



static void dispc_clear_irqstatus(u32 mask);

static bool dispc_mgr_is_enabled(enum omap_channel channel);

static void dispc_clear_irqstatus(u32 mask);



static inline void dispc_write_reg(const u16 idx, u32 val)

{

	__raw_writel(val, dispc.base + idx);
@@ -581,7 +585,6 @@ int dispc_runtime_get(void) 
	WARN_ON(r < 0);

	return r < 0 ? r : 0;

}

EXPORT_SYMBOL(dispc_runtime_get);



void dispc_runtime_put(void)

{
@@ -592,54 +595,48 @@ void dispc_runtime_put(void) 
	r = pm_runtime_put_sync(&dispc.pdev->dev);

	WARN_ON(r < 0 && r != -ENOSYS);

}

EXPORT_SYMBOL(dispc_runtime_put);



u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)

static u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)

{

	return mgr_desc[channel].vsync_irq;

}

EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);



u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)

static u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)

{

	if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)

		return 0;



	return mgr_desc[channel].framedone_irq;

}

EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);



u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)

static u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)

{

	return mgr_desc[channel].sync_lost_irq;

}

EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);



u32 dispc_wb_get_framedone_irq(void)

{

	return DISPC_IRQ_FRAMEDONEWB;

}



void dispc_mgr_enable(enum omap_channel channel, bool enable)

static void dispc_mgr_enable(enum omap_channel channel, bool enable)

{

	mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);

	/* flush posted write */

	mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);

}

EXPORT_SYMBOL(dispc_mgr_enable);



static bool dispc_mgr_is_enabled(enum omap_channel channel)

{

	return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);

}



bool dispc_mgr_go_busy(enum omap_channel channel)

static bool dispc_mgr_go_busy(enum omap_channel channel)

{

	return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;

}

EXPORT_SYMBOL(dispc_mgr_go_busy);



void dispc_mgr_go(enum omap_channel channel)

static void dispc_mgr_go(enum omap_channel channel)

{

	WARN_ON(!dispc_mgr_is_enabled(channel));

	WARN_ON(dispc_mgr_go_busy(channel));
@@ -648,7 +645,6 @@ void dispc_mgr_go(enum omap_channel channel) 


	mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);

}

EXPORT_SYMBOL(dispc_mgr_go);



bool dispc_wb_go_busy(void)

{
@@ -997,7 +993,7 @@ static void dispc_ovl_configure_burst_type(enum omap_plane plane, 
		REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);

}



void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)

static void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)

{

	int shift;

	u32 val;
@@ -1057,7 +1053,6 @@ void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel) 
	}

	dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);

}

EXPORT_SYMBOL(dispc_ovl_set_channel_out);



static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)

{
@@ -1135,17 +1130,15 @@ static u32 dispc_ovl_get_burst_size(enum omap_plane plane) 
	return unit * 8;

}



enum omap_color_mode dispc_ovl_get_color_modes(enum omap_plane plane)

static enum omap_color_mode dispc_ovl_get_color_modes(enum omap_plane plane)

{

	return dss_feat_get_supported_color_modes(plane);

}

EXPORT_SYMBOL(dispc_ovl_get_color_modes);



int dispc_get_num_ovls(void)

static int dispc_get_num_ovls(void)

{

	return dss_feat_get_num_ovls();

}

EXPORT_SYMBOL(dispc_get_num_ovls);



static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)

{
@@ -2829,9 +2822,8 @@ static int dispc_ovl_setup_common(enum omap_plane plane, 
	return 0;

}



int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,

		bool replication, const struct videomode *vm,

		bool mem_to_mem)

static int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,

		bool replication, const struct videomode *vm, bool mem_to_mem)

{

	int r;

	enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
@@ -2853,7 +2845,6 @@ int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, 


	return r;

}

EXPORT_SYMBOL(dispc_ovl_setup);



int dispc_wb_setup(const struct omap_dss_writeback_info *wi,

		bool mem_to_mem, const struct videomode *vm)
@@ -2923,7 +2914,7 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi, 
	return r;

}



int dispc_ovl_enable(enum omap_plane plane, bool enable)

static int dispc_ovl_enable(enum omap_plane plane, bool enable)

{

	DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
@@ -2931,19 +2922,16 @@ int dispc_ovl_enable(enum omap_plane plane, bool enable) 


	return 0;

}

EXPORT_SYMBOL(dispc_ovl_enable);



bool dispc_ovl_enabled(enum omap_plane plane)

static bool dispc_ovl_enabled(enum omap_plane plane)

{

	return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);

}

EXPORT_SYMBOL(dispc_ovl_enabled);



enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel)

static enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel)

{

	return dss_feat_get_supported_outputs(channel);

}

EXPORT_SYMBOL(dispc_mgr_get_supported_outputs);



void dispc_wb_enable(bool enable)

{
@@ -2979,11 +2967,10 @@ void dispc_pck_free_enable(bool enable) 
	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);

}



int dispc_get_num_mgrs(void)

static int dispc_get_num_mgrs(void)

{

	return dss_feat_get_num_mgrs();

}

EXPORT_SYMBOL(dispc_get_num_mgrs);



static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)

{
@@ -3033,7 +3020,7 @@ static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, 
		REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);

}



void dispc_mgr_setup(enum omap_channel channel,

static void dispc_mgr_setup(enum omap_channel channel,

		const struct omap_overlay_manager_info *info)

{

	dispc_mgr_set_default_color(channel, info->default_color);
@@ -3046,7 +3033,6 @@ void dispc_mgr_setup(enum omap_channel channel, 
		dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);

	}

}

EXPORT_SYMBOL(dispc_mgr_setup);



static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)

{
@@ -3107,7 +3093,7 @@ static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable) 
	mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);

}



void dispc_mgr_set_lcd_config(enum omap_channel channel,

static void dispc_mgr_set_lcd_config(enum omap_channel channel,

		const struct dss_lcd_mgr_config *config)

{

	dispc_mgr_set_io_pad_mode(config->io_pad_mode);
@@ -3123,7 +3109,6 @@ void dispc_mgr_set_lcd_config(enum omap_channel channel, 


	dispc_mgr_set_lcd_type_tft(channel);

}

EXPORT_SYMBOL(dispc_mgr_set_lcd_config);



static bool _dispc_mgr_size_ok(u16 width, u16 height)

{
@@ -3254,7 +3239,7 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, 
}



/* change name to mode? */

void dispc_mgr_set_timings(enum omap_channel channel,

static void dispc_mgr_set_timings(enum omap_channel channel,

			   const struct videomode *vm)

{

	unsigned xtot, ytot;
@@ -3301,7 +3286,6 @@ void dispc_mgr_set_timings(enum omap_channel channel, 


	dispc_mgr_set_size(channel, t.hactive, t.vactive);

}

EXPORT_SYMBOL(dispc_mgr_set_timings);



static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,

		u16 pck_div)
@@ -3781,25 +3765,22 @@ int dispc_mgr_get_clock_div(enum omap_channel channel, 
	return 0;

}



u32 dispc_read_irqstatus(void)

static u32 dispc_read_irqstatus(void)

{

	return dispc_read_reg(DISPC_IRQSTATUS);

}

EXPORT_SYMBOL(dispc_read_irqstatus);



void dispc_clear_irqstatus(u32 mask)

static void dispc_clear_irqstatus(u32 mask)

{

	dispc_write_reg(DISPC_IRQSTATUS, mask);

}

EXPORT_SYMBOL(dispc_clear_irqstatus);



u32 dispc_read_irqenable(void)

static u32 dispc_read_irqenable(void)

{

	return dispc_read_reg(DISPC_IRQENABLE);

}

EXPORT_SYMBOL(dispc_read_irqenable);



void dispc_write_irqenable(u32 mask)

static void dispc_write_irqenable(u32 mask)

{

	u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
@@ -3808,7 +3789,6 @@ void dispc_write_irqenable(u32 mask) 


	dispc_write_reg(DISPC_IRQENABLE, mask);

}

EXPORT_SYMBOL(dispc_write_irqenable);



void dispc_enable_sidle(void)

{
@@ -3820,7 +3800,7 @@ void dispc_disable_sidle(void) 
	REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);	/* SIDLEMODE: no idle */

}



u32 dispc_mgr_gamma_size(enum omap_channel channel)

static u32 dispc_mgr_gamma_size(enum omap_channel channel)

{

	const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
@@ -3829,7 +3809,6 @@ u32 dispc_mgr_gamma_size(enum omap_channel channel) 


	return gdesc->len;

}

EXPORT_SYMBOL(dispc_mgr_gamma_size);



static void dispc_mgr_write_gamma_table(enum omap_channel channel)

{
@@ -3874,7 +3853,7 @@ static const struct drm_color_lut dispc_mgr_gamma_default_lut[] = { 
	{ .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, },

};



void dispc_mgr_set_gamma(enum omap_channel channel,

static void dispc_mgr_set_gamma(enum omap_channel channel,

			 const struct drm_color_lut *lut,

			 unsigned int length)

{
@@ -3920,7 +3899,6 @@ void dispc_mgr_set_gamma(enum omap_channel channel, 
	if (dispc.is_enabled)

		dispc_mgr_write_gamma_table(channel);

}

EXPORT_SYMBOL(dispc_mgr_set_gamma);



static int dispc_init_gamma_tables(void)

{
@@ -4167,7 +4145,7 @@ static irqreturn_t dispc_irq_handler(int irq, void *arg) 
	return dispc.user_handler(irq, dispc.user_data);

}



int dispc_request_irq(irq_handler_t handler, void *dev_id)

static int dispc_request_irq(irq_handler_t handler, void *dev_id)

{

	int r;
@@ -4189,16 +4167,14 @@ int dispc_request_irq(irq_handler_t handler, void *dev_id) 


	return r;

}

EXPORT_SYMBOL(dispc_request_irq);



void dispc_free_irq(void *dev_id)

static void dispc_free_irq(void *dev_id)

{

	devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);



	dispc.user_handler = NULL;

	dispc.user_data = NULL;

}

EXPORT_SYMBOL(dispc_free_irq);



/*

 * Workaround for errata i734 in DSS dispc

drivers/gpu/drm/omapdrm/dss/dss.h

+3 −0
Original line number Diff line number Diff line
@@ -337,6 +337,9 @@ int dispc_init_platform_driver(void) __init; 
void dispc_uninit_platform_driver(void);

void dispc_dump_clocks(struct seq_file *s);



int dispc_runtime_get(void);

void dispc_runtime_put(void);



void dispc_enable_sidle(void);

void dispc_disable_sidle(void);

drivers/gpu/drm/omapdrm/dss/omapdss.h

+0 −42
Original line number Diff line number Diff line
@@ -849,48 +849,6 @@ void omapdss_set_is_initialized(bool set); 
struct device_node *dss_of_port_get_parent_device(struct device_node *port);

u32 dss_of_port_get_port_number(struct device_node *port);



u32 dispc_read_irqstatus(void);

void dispc_clear_irqstatus(u32 mask);

u32 dispc_read_irqenable(void);

void dispc_write_irqenable(u32 mask);



int dispc_request_irq(irq_handler_t handler, void *dev_id);

void dispc_free_irq(void *dev_id);



int dispc_runtime_get(void);

void dispc_runtime_put(void);



int dispc_get_num_ovls(void);

int dispc_get_num_mgrs(void);



void dispc_mgr_enable(enum omap_channel channel, bool enable);

u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);

u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);

u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);

bool dispc_mgr_go_busy(enum omap_channel channel);

void dispc_mgr_go(enum omap_channel channel);

void dispc_mgr_set_lcd_config(enum omap_channel channel,

		const struct dss_lcd_mgr_config *config);

void dispc_mgr_set_timings(enum omap_channel channel,

		const struct videomode *vm);

void dispc_mgr_setup(enum omap_channel channel,

		const struct omap_overlay_manager_info *info);

enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel);

u32 dispc_mgr_gamma_size(enum omap_channel channel);

void dispc_mgr_set_gamma(enum omap_channel channel,

			 const struct drm_color_lut *lut,

			 unsigned int length);



int dispc_ovl_enable(enum omap_plane plane, bool enable);

bool dispc_ovl_enabled(enum omap_plane plane);

void dispc_ovl_set_channel_out(enum omap_plane plane,

		enum omap_channel channel);

int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,

		bool replication, const struct videomode *vm, bool mem_to_mem);

enum omap_color_mode dispc_ovl_get_color_modes(enum omap_plane plane);



enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel);



struct dss_mgr_ops {

	int (*connect)(enum omap_channel channel,

		struct omap_dss_device *dst);