Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

CONFIG_TRANSPARENT_HUGEPAGE=y

CONFIG_CMA=y

CONFIG_XEN=y

CONFIG_CMDLINE="console=ttyAMA0"

# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set

CONFIG_COMPAT=y

CONFIG_CPU_IDLE=y

CONFIG_ARM_CPUIDLE=y

CONFIG_CPU_FREQ=y

CONFIG_ARM_BIG_LITTLE_CPUFREQ=y

CONFIG_ARM_SCPI_CPUFREQ=y

CONFIG_NET=y

CONFIG_PACKET=y

CONFIG_UNIX=y

CONFIG_IP_PNP=y

CONFIG_IP_PNP_DHCP=y

CONFIG_IP_PNP_BOOTP=y

# CONFIG_INET_LRO is not set

# CONFIG_IPV6 is not set

CONFIG_BPF_JIT=y

# CONFIG_WIRELESS is not set

CONFIG_SERIAL_MVEBU_UART=y

CONFIG_VIRTIO_CONSOLE=y

# CONFIG_HW_RANDOM is not set

CONFIG_I2C=y

CONFIG_I2C_CHARDEV=y

CONFIG_I2C_DESIGNWARE_PLATFORM=y

CONFIG_I2C_MV64XXX=y

CONFIG_I2C_QUP=y

CONFIG_I2C_TEGRA=y

CONFIG_I2C_UNIPHIER_F=y

CONFIG_I2C_RCAR=y

CONFIG_SPI=y

CONFIG_SPI_PL022=y

CONFIG_SPI_QUP=y

CONFIG_SPMI=y

CONFIG_PINCTRL_SINGLE=y

CONFIG_PINCTRL_MSM8916=y

CONFIG_PINCTRL_QCOM_SPMI_PMIC=y

CONFIG_GPIO_SYSFS=y

CONFIG_USB_OHCI_HCD=y

CONFIG_USB_OHCI_HCD_PLATFORM=y

CONFIG_USB_STORAGE=y

CONFIG_USB_DWC2=y

CONFIG_USB_CHIPIDEA=y

CONFIG_USB_CHIPIDEA_UDC=y

CONFIG_USB_CHIPIDEA_HOST=y

CONFIG_USB_ULPI=y

CONFIG_USB_GADGET=y

CONFIG_MMC=y

CONFIG_MMC_BLOCK_MINORS=16

CONFIG_MMC_BLOCK_MINORS=32

CONFIG_MMC_ARMMMCI=y

CONFIG_MMC_SDHCI=y

CONFIG_MMC_SDHCI_PLTFM=y

CONFIG_MMC_SDHCI_TEGRA=y

CONFIG_MMC_SDHCI_MSM=y

CONFIG_MMC_SPI=y

CONFIG_MMC_SUNXI=y

CONFIG_MMC_DW=y

CONFIG_MMC_DW_EXYNOS=y

CONFIG_MMC_BLOCK_MINORS=16

CONFIG_MMC_DW_K3=y

CONFIG_MMC_SUNXI=y

CONFIG_NEW_LEDS=y

CONFIG_LEDS_CLASS=y

CONFIG_LEDS_GPIO=y

CONFIG_LEDS_SYSCON=y

CONFIG_LEDS_TRIGGERS=y

CONFIG_LEDS_TRIGGER_HEARTBEAT=y

CONFIG_RTC_DRV_SUN6I=y

CONFIG_RTC_DRV_XGENE=y

CONFIG_DMADEVICES=y

CONFIG_QCOM_BAM_DMA=y

CONFIG_TEGRA20_APB_DMA=y

CONFIG_QCOM_BAM_DMA=y

CONFIG_RCAR_DMAC=y

CONFIG_VFIO=y

CONFIG_VFIO_PCI=y

CONFIG_VIRTIO_MMIO=y

CONFIG_XEN_GNTDEV=y

CONFIG_XEN_GRANT_DEV_ALLOC=y

CONFIG_COMMON_CLK_SCPI=y

CONFIG_COMMON_CLK_CS2000_CP=y

CONFIG_COMMON_CLK_QCOM=y

CONFIG_MSM_GCC_8916=y

CONFIG_HWSPINLOCK_QCOM=y

CONFIG_MAILBOX=y

CONFIG_ARM_MHU=y

CONFIG_HI6220_MBOX=y

CONFIG_ARM_SMMU=y

CONFIG_QCOM_SMEM=y

CONFIG_QCOM_SMD=y

CONFIG_QCOM_SMD_RPM=y

CONFIG_ARCH_TEGRA_132_SOC=y

CONFIG_ARCH_TEGRA_210_SOC=y

CONFIG_HISILICON_IRQ_MBIGEN=y

CONFIG_EXTCON_USB_GPIO=y

CONFIG_COMMON_RESET_HI6220=y

CONFIG_PHY_RCAR_GEN3_USB2=y

CONFIG_PHY_HI6220_USB=y

CONFIG_PHY_XGENE=y

CONFIG_ARM_SCPI_PROTOCOL=y

CONFIG_EXT2_FS=y

CONFIG_EXT3_FS=y

CONFIG_FANOTIFY=y

CONFIG_VFAT_FS=y

CONFIG_TMPFS=y

CONFIG_HUGETLBFS=y

CONFIG_CONFIGFS_FS=y

CONFIG_EFIVAR_FS=y

CONFIG_SQUASHFS=y

CONFIG_NFS_FS=y

#include <asm/kvm.h>

#include <asm/kvm_asm.h>

#include <asm/kvm_mmio.h>

#include <asm/kvm_perf_event.h>

#define __KVM_HAVE_ARCH_INTC_INITIALIZED

#include <linux/compiler.h>

#include <linux/kvm_host.h>

#include <asm/kvm_mmu.h>

#include <asm/kvm_perf_event.h>

#include <asm/sysreg.h>

#define __hyp_text __section(.hyp.text) notrace

/*

 * Copyright (C) 2012 ARM Ltd.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */

#ifndef __ASM_KVM_PERF_EVENT_H

#define __ASM_KVM_PERF_EVENT_H

#define	ARMV8_PMU_MAX_COUNTERS	32

#define	ARMV8_PMU_COUNTER_MASK	(ARMV8_PMU_MAX_COUNTERS - 1)

/*

 * Per-CPU PMCR: config reg

 */

#define ARMV8_PMU_PMCR_E	(1 << 0) /* Enable all counters */

#define ARMV8_PMU_PMCR_P	(1 << 1) /* Reset all counters */

#define ARMV8_PMU_PMCR_C	(1 << 2) /* Cycle counter reset */

#define ARMV8_PMU_PMCR_D	(1 << 3) /* CCNT counts every 64th cpu cycle */

#define ARMV8_PMU_PMCR_X	(1 << 4) /* Export to ETM */

#define ARMV8_PMU_PMCR_DP	(1 << 5) /* Disable CCNT if non-invasive debug*/

/* Determines which bit of PMCCNTR_EL0 generates an overflow */

#define ARMV8_PMU_PMCR_LC	(1 << 6)

#define	ARMV8_PMU_PMCR_N_SHIFT	11	 /* Number of counters supported */

#define	ARMV8_PMU_PMCR_N_MASK	0x1f

#define	ARMV8_PMU_PMCR_MASK	0x7f	 /* Mask for writable bits */

/*

 * PMOVSR: counters overflow flag status reg

 */

#define	ARMV8_PMU_OVSR_MASK		0xffffffff	/* Mask for writable bits */

#define	ARMV8_PMU_OVERFLOWED_MASK	ARMV8_PMU_OVSR_MASK

/*

 * PMXEVTYPER: Event selection reg

 */

#define	ARMV8_PMU_EVTYPE_MASK	0xc80003ff	/* Mask for writable bits */

#define	ARMV8_PMU_EVTYPE_EVENT	0x3ff		/* Mask for EVENT bits */

#define ARMV8_PMU_EVTYPE_EVENT_SW_INCR	0	/* Software increment event */

/*

 * Event filters for PMUv3

 */

#define	ARMV8_PMU_EXCLUDE_EL1	(1 << 31)

#define	ARMV8_PMU_EXCLUDE_EL0	(1 << 30)

#define	ARMV8_PMU_INCLUDE_EL2	(1 << 27)

/*

 * PMUSERENR: user enable reg

 */

#define ARMV8_PMU_USERENR_MASK	0xf		/* Mask for writable bits */

#define ARMV8_PMU_USERENR_EN	(1 << 0) /* PMU regs can be accessed at EL0 */

#define ARMV8_PMU_USERENR_SW	(1 << 1) /* PMSWINC can be written at EL0 */

#define ARMV8_PMU_USERENR_CR	(1 << 2) /* Cycle counter can be read at EL0 */

#define ARMV8_PMU_USERENR_ER	(1 << 3) /* Event counter can be read at EL0 */

#endif

#ifdef CONFIG_CPU_BIG_ENDIAN

#define CONFIG_CPU_ENDIAN_BE8 CONFIG_CPU_BIG_ENDIAN

#endif

#include <../../arm/include/asm/opcodes.h>