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Commit 4fd89226 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2017-05-18-1' of... 

Merge tag 'drm-intel-fixes-2017-05-18-1' of git://anongit.freedesktop.org/git/drm-intel into drm-fixes

drm/i915 fixes for v4.12-rc2

* tag 'drm-intel-fixes-2017-05-18-1' of git://anongit.freedesktop.org/git/drm-intel:
  drm/i915: don't do allocate_va_range again on PIN_UPDATE
  drm/i915: Fix rawclk readout for g4x
  drm/i915: Fix runtime PM for LPE audio
  drm/i915/glk: Fix DSI "*ERROR* ULPS is still active" messages
  drm/i915/gvt: avoid unnecessary vgpu switch
  drm/i915/gvt: not to restore in-context mmio
  drm/i915/gvt: fix typo: "supporte" -> "support"
parents e6296126 2f720aac

drivers/gpu/drm/i915/gvt/handlers.c

+1 −1
Original line number Diff line number Diff line
@@ -1244,7 +1244,7 @@ static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 
	mode = vgpu_vreg(vgpu, offset);



	if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {

		WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n",

		WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n",

				vgpu->id);

		return 0;

	}

drivers/gpu/drm/i915/gvt/render.c

+3 −0
Original line number Diff line number Diff line
@@ -340,6 +340,9 @@ void intel_gvt_restore_render_mmio(struct intel_vgpu *vgpu, int ring_id) 
		} else

			v = mmio->value;



		if (mmio->in_context)

			continue;



		I915_WRITE(mmio->reg, v);

		POSTING_READ(mmio->reg);

drivers/gpu/drm/i915/gvt/sched_policy.c

+6 −2
Original line number Diff line number Diff line
@@ -129,9 +129,13 @@ static void try_to_schedule_next_vgpu(struct intel_gvt *gvt) 
	struct vgpu_sched_data *vgpu_data;

	ktime_t cur_time;



	/* no target to schedule */

	if (!scheduler->next_vgpu)

	/* no need to schedule if next_vgpu is the same with current_vgpu,

	 * let scheduler chose next_vgpu again by setting it to NULL.

	 */

	if (scheduler->next_vgpu == scheduler->current_vgpu) {

		scheduler->next_vgpu = NULL;

		return;

	}



	/*

	 * after the flag is set, workload dispatch thread will

drivers/gpu/drm/i915/i915_gem_gtt.c

+8 −4
Original line number Diff line number Diff line
@@ -195,9 +195,12 @@ static int ppgtt_bind_vma(struct i915_vma *vma, 
	u32 pte_flags;

	int ret;



	ret = vma->vm->allocate_va_range(vma->vm, vma->node.start, vma->size);

	if (!(vma->flags & I915_VMA_LOCAL_BIND)) {

		ret = vma->vm->allocate_va_range(vma->vm, vma->node.start,

						 vma->size);

		if (ret)

			return ret;

	}



	vma->pages = vma->obj->mm.pages;
@@ -2306,7 +2309,8 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma, 
	if (flags & I915_VMA_LOCAL_BIND) {

		struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt;



		if (appgtt->base.allocate_va_range) {

		if (!(vma->flags & I915_VMA_LOCAL_BIND) &&

		    appgtt->base.allocate_va_range) {

			ret = appgtt->base.allocate_va_range(&appgtt->base,

							     vma->node.start,

							     vma->node.size);

drivers/gpu/drm/i915/i915_reg.h

+7 −3
Original line number Diff line number Diff line
@@ -3051,10 +3051,14 @@ enum skl_disp_power_wells { 
#define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */

#define CLKCFG_FSB_800					(2 << 0)	/* hrawclk 200 */

#define CLKCFG_FSB_1067					(6 << 0)	/* hrawclk 266 */

#define CLKCFG_FSB_1067_ALT				(0 << 0)	/* hrawclk 266 */

#define CLKCFG_FSB_1333					(7 << 0)	/* hrawclk 333 */

/* Note, below two are guess */

#define CLKCFG_FSB_1600					(4 << 0)	/* hrawclk 400 */

#define CLKCFG_FSB_1600_ALT				(0 << 0)	/* hrawclk 400 */

/*

 * Note that on at least on ELK the below value is reported for both

 * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet

 * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz.

 */

#define CLKCFG_FSB_1333_ALT				(4 << 0)	/* hrawclk 333 */

#define CLKCFG_FSB_MASK					(7 << 0)

#define CLKCFG_MEM_533					(1 << 4)

#define CLKCFG_MEM_667					(2 << 4)