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Commit 4e80519e authored by Imre Deak's avatar Imre Deak Committed by Daniel Vetter
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drm/i915: vlv: setup RPS min/max frequencies once during init time 



When enabling runtime PM on VLV, GT power save enabling becomes relatively
frequent, so optimize it a bit.

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 9486db61

drivers/gpu/drm/i915/intel_pm.c

+41 −25
Original line number Diff line number Diff line
@@ -3701,6 +3701,45 @@ static void valleyview_cleanup_pctx(struct drm_device *dev) 
	dev_priv->vlv_pctx = NULL;

}



static void valleyview_init_gt_powersave(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	valleyview_setup_pctx(dev);



	mutex_lock(&dev_priv->rps.hw_lock);



	dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);

	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;

	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",

			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),

			 dev_priv->rps.max_freq);



	dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);

	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",

			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),

			 dev_priv->rps.efficient_freq);



	dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);

	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",

			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),

			 dev_priv->rps.min_freq);



	/* Preserve min/max settings in case of re-init */

	if (dev_priv->rps.max_freq_softlimit == 0)

		dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;



	if (dev_priv->rps.min_freq_softlimit == 0)

		dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;



	mutex_unlock(&dev_priv->rps.hw_lock);

}



static void valleyview_cleanup_gt_powersave(struct drm_device *dev)

{

	valleyview_cleanup_pctx(dev);

}



static void valleyview_enable_rps(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3767,29 +3806,6 @@ static void valleyview_enable_rps(struct drm_device *dev) 
			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),

			 dev_priv->rps.cur_freq);



	dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);

	dev_priv->rps.rp0_freq  = dev_priv->rps.max_freq;

	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",

			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),

			 dev_priv->rps.max_freq);



	dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);

	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",

			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),

			 dev_priv->rps.efficient_freq);



	dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);

	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",

			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),

			 dev_priv->rps.min_freq);



	/* Preserve min/max settings in case of re-init */

	if (dev_priv->rps.max_freq_softlimit == 0)

		dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;



	if (dev_priv->rps.min_freq_softlimit == 0)

		dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;



	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",

			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),

			 dev_priv->rps.efficient_freq);
@@ -4533,13 +4549,13 @@ void intel_init_gt_powersave(struct drm_device *dev) 
	i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);



	if (IS_VALLEYVIEW(dev))

		valleyview_setup_pctx(dev);

		valleyview_init_gt_powersave(dev);

}



void intel_cleanup_gt_powersave(struct drm_device *dev)

{

	if (IS_VALLEYVIEW(dev))

		valleyview_cleanup_pctx(dev);

		valleyview_cleanup_gt_powersave(dev);

}



void intel_disable_gt_powersave(struct drm_device *dev)