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Commit 4e7b4997 authored by Yaniv Rosner's avatar Yaniv Rosner Committed by David S. Miller
Browse files

bnx2x: Add support for 20G-KR2 



Signed-off-by: default avatarYaniv Rosner <yanivr@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent b884d95b

drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h

+2 −0
Original line number Diff line number Diff line
@@ -2167,6 +2167,8 @@ struct shmem2_region { 
	u32 reserved2;				/* Offset 0x148 */

	u32 reserved3;				/* Offset 0x14C */

	u32 reserved4;				/* Offset 0x150 */

	u32 link_attr_sync[PORT_MAX];		/* Offset 0x154 */

	#define LINK_ATTR_SYNC_KR2_ENABLE	(1<<0)

};

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

+334 −32

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h

+2 −0
Original line number Diff line number Diff line
@@ -347,6 +347,8 @@ struct link_vars { 
	u8 rx_tx_asic_rst;

	u8 turn_to_run_wc_rt;

	u16 rsrv2;

	/* The same definitions as the shmem2 parameter */

	u32 link_attr_sync;

};



/***********************************************************/

drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h

+27 −2
Original line number Diff line number Diff line
@@ -5498,6 +5498,7 @@ 
#define XMAC_CTRL_REG_RX_EN					 (0x1<<1)

#define XMAC_CTRL_REG_SOFT_RESET				 (0x1<<6)

#define XMAC_CTRL_REG_TX_EN					 (0x1<<0)

#define XMAC_CTRL_REG_XLGMII_ALIGN_ENB				 (0x1<<7)

#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN				 (0x1<<18)

#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN				 (0x1<<17)

#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON			 (0x1<<1)
@@ -5518,11 +5519,14 @@ 
#define XMAC_REG_PAUSE_CTRL					 0x68

#define XMAC_REG_PFC_CTRL					 0x70

#define XMAC_REG_PFC_CTRL_HI					 0x74

#define XMAC_REG_RX_LSS_CTRL					 0x50

#define XMAC_REG_RX_LSS_STATUS					 0x58

/* [RW 14] Maximum packet size in receive direction; exclusive of preamble &

 * CRC in strip mode */

#define XMAC_REG_RX_MAX_SIZE					 0x40

#define XMAC_REG_TX_CTRL					 0x20

#define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE		 (0x1<<0)

#define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE		 (0x1<<1)

/* [RW 16] Indirect access to the XX table of the XX protection mechanism.

   The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -

   header pointer. */
@@ -6688,6 +6692,7 @@ 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI	0x1B00

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS	0x1E00

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI	0x1F00

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2	0x3900





#define MDIO_REG_BANK_10G_PARALLEL_DETECT		0x8130
@@ -7062,7 +7067,8 @@ Theotherbitsarereservedandshouldbezero*/ 
#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2	0x12

#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY	0x4000

#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ		0x8000

#define MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150  0x96

#define MDIO_WC_REG_PCS_STATUS2				0x0021

#define MDIO_WC_REG_PMD_KR_CONTROL			0x0096

#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL		0x8000

#define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1		0x800e

#define MDIO_WC_REG_XGXSBLK1_DESKEW			0x8010
@@ -7094,6 +7100,7 @@ Theotherbitsarereservedandshouldbezero*/ 
#define MDIO_WC_REG_PAR_DET_10G_STATUS			0x8130

#define MDIO_WC_REG_PAR_DET_10G_CTRL			0x8131

#define MDIO_WC_REG_XGXS_X2_CONTROL2			0x8141

#define MDIO_WC_REG_XGXS_X2_CONTROL3			0x8142

#define MDIO_WC_REG_XGXS_RX_LN_SWAP1			0x816B

#define MDIO_WC_REG_XGXS_TX_LN_SWAP1			0x8169

#define MDIO_WC_REG_GP2_STATUS_GP_2_0			0x81d0
@@ -7128,6 +7135,7 @@ Theotherbitsarereservedandshouldbezero*/ 
#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET		0x0a

#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK		0x7c00

#define MDIO_WC_REG_TX_FIR_TAP_ENABLE		0x8000

#define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP		0x82e2

#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL	0x82e3

#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL	0x82e6

#define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL	0x82e7
@@ -7145,9 +7153,16 @@ Theotherbitsarereservedandshouldbezero*/ 
#define MDIO_WC_REG_DIGITAL4_MISC5			0x833e

#define MDIO_WC_REG_DIGITAL5_MISC6			0x8345

#define MDIO_WC_REG_DIGITAL5_MISC7			0x8349

#define MDIO_WC_REG_DIGITAL5_LINK_STATUS		0x834d

#define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED		0x834e

#define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL		0x8350

#define MDIO_WC_REG_CL49_USERB0_CTRL			0x8368

#define MDIO_WC_REG_CL73_USERB0_CTRL			0x8370

#define MDIO_WC_REG_CL73_USERB0_USTAT			0x8371

#define MDIO_WC_REG_CL73_BAM_CTRL1			0x8372

#define MDIO_WC_REG_CL73_BAM_CTRL2			0x8373

#define MDIO_WC_REG_CL73_BAM_CTRL3			0x8374

#define MDIO_WC_REG_CL73_BAM_CODE_FIELD			0x837b

#define MDIO_WC_REG_EEE_COMBO_CONTROL0			0x8390

#define MDIO_WC_REG_TX66_CONTROL			0x83b0

#define MDIO_WC_REG_RX66_CONTROL			0x83c0
@@ -7161,7 +7176,17 @@ Theotherbitsarereservedandshouldbezero*/ 
#define MDIO_WC_REG_RX66_SCW3_MASK			0x83c9

#define MDIO_WC_REG_FX100_CTRL1				0x8400

#define MDIO_WC_REG_FX100_CTRL3				0x8402



#define MDIO_WC_REG_CL82_USERB1_TX_CTRL5		0x8436

#define MDIO_WC_REG_CL82_USERB1_TX_CTRL6		0x8437

#define MDIO_WC_REG_CL82_USERB1_TX_CTRL7		0x8438

#define MDIO_WC_REG_CL82_USERB1_TX_CTRL9		0x8439

#define MDIO_WC_REG_CL82_USERB1_RX_CTRL10		0x843a

#define MDIO_WC_REG_CL82_USERB1_RX_CTRL11		0x843b

#define MDIO_WC_REG_ETA_CL73_OUI1			0x8453

#define MDIO_WC_REG_ETA_CL73_OUI2			0x8454

#define MDIO_WC_REG_ETA_CL73_OUI3			0x8455

#define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE		0x8456

#define MDIO_WC_REG_ETA_CL73_LD_UD_CODE			0x8457

#define MDIO_WC_REG_MICROBLK_CMD			0xffc2

#define MDIO_WC_REG_MICROBLK_DL_STATUS			0xffc5

#define MDIO_WC_REG_MICROBLK_CMD3			0xffcc