Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4e4b3563 authored by Russell King's avatar Russell King
Browse files

drm/armada: clean up SPU_ADV_REG 



Rather than writing all bits of SPU_ADV_REG on modeset, only write
what we need to change, and initialise the register in the variant
initialisation.

Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
parent a61c3922

drivers/gpu/drm/armada/armada_510.c

+4 −1
Original line number Original line Diff line number Diff line
@@ -27,6 +27,10 @@ static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev) 
	/* Lower the watermark so to eliminate jitter at higher bandwidths */

	/* Lower the watermark so to eliminate jitter at higher bandwidths */

	armada_updatel(0x20, (1 << 11) | 0xff, dcrtc->base + LCD_CFG_RDREG4F);

	armada_updatel(0x20, (1 << 11) | 0xff, dcrtc->base + LCD_CFG_RDREG4F);





	/* Initialise SPU register */

	writel_relaxed(ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,

		       dcrtc->base + LCD_SPU_ADV_REG);



	return 0;

	return 0;

}

}
@@ -77,7 +81,6 @@ static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc, 




const struct armada_variant armada510_ops = {

const struct armada_variant armada510_ops = {

	.has_spu_adv_reg = true,

	.has_spu_adv_reg = true,

	.spu_adv_reg = ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,

	.init = armada510_crtc_init,

	.init = armada510_crtc_init,

	.compute_clock = armada510_crtc_compute_clock,

	.compute_clock = armada510_crtc_compute_clock,

};
 
};

drivers/gpu/drm/armada/armada_crtc.c

+4 −7
Original line number Original line Diff line number Diff line
@@ -463,17 +463,15 @@ static void armada_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 
				    adj->crtc_htotal;

				    adj->crtc_htotal;

	dcrtc->v[1].spu_v_porch = tm << 16 | bm;

	dcrtc->v[1].spu_v_porch = tm << 16 | bm;

	val = adj->crtc_hsync_start;

	val = adj->crtc_hsync_start;

	dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |

	dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN;

		dcrtc->variant->spu_adv_reg;





	if (interlaced) {

	if (interlaced) {

		/* Odd interlaced frame */

		/* Odd interlaced frame */

		val -= adj->crtc_htotal / 2;

		dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN;

		dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +

		dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +

						(1 << 16);

						(1 << 16);

		dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;

		dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;

		val = adj->crtc_hsync_start - adj->crtc_htotal / 2;

		dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |

			dcrtc->variant->spu_adv_reg;

	} else {

	} else {

		dcrtc->v[0] = dcrtc->v[1];

		dcrtc->v[0] = dcrtc->v[1];

	}

	}
@@ -486,11 +484,10 @@ static void armada_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 
	armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,

	armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,

			   LCD_SPUT_V_H_TOTAL);

			   LCD_SPUT_V_H_TOTAL);





	if (dcrtc->variant->has_spu_adv_reg) {

	if (dcrtc->variant->has_spu_adv_reg)

		armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,

		armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,

				     ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |

				     ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |

				     ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);

				     ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);

	}





	val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;

	val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;

	armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);

	armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);

drivers/gpu/drm/armada/armada_drm.h

+0 −1
Original line number Original line Diff line number Diff line
@@ -42,7 +42,6 @@ struct armada_private; 




struct armada_variant {

struct armada_variant {

	bool has_spu_adv_reg;

	bool has_spu_adv_reg;

	uint32_t spu_adv_reg;

	int (*init)(struct armada_crtc *, struct device *);

	int (*init)(struct armada_crtc *, struct device *);

	int (*compute_clock)(struct armada_crtc *,

	int (*compute_clock)(struct armada_crtc *,

			     const struct drm_display_mode *,

			     const struct drm_display_mode *,